GB2089117B - Improvements in and relating to the manufacure of wafer scale integrated circuits - Google Patents
Improvements in and relating to the manufacure of wafer scale integrated circuitsInfo
- Publication number
- GB2089117B GB2089117B GB8039046A GB8039046A GB2089117B GB 2089117 B GB2089117 B GB 2089117B GB 8039046 A GB8039046 A GB 8039046A GB 8039046 A GB8039046 A GB 8039046A GB 2089117 B GB2089117 B GB 2089117B
- Authority
- GB
- United Kingdom
- Prior art keywords
- manufacure
- relating
- integrated circuits
- scale integrated
- wafer scale
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8039046A GB2089117B (en) | 1980-12-05 | 1980-12-05 | Improvements in and relating to the manufacure of wafer scale integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8039046A GB2089117B (en) | 1980-12-05 | 1980-12-05 | Improvements in and relating to the manufacure of wafer scale integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2089117A GB2089117A (en) | 1982-06-16 |
GB2089117B true GB2089117B (en) | 1984-10-17 |
Family
ID=10517775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8039046A Expired GB2089117B (en) | 1980-12-05 | 1980-12-05 | Improvements in and relating to the manufacure of wafer scale integrated circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2089117B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5349219A (en) * | 1989-06-15 | 1994-09-20 | Fujitsu Limited | Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device |
EP0403898A3 (en) * | 1989-06-15 | 1991-08-07 | Fujitsu Limited | Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device |
US5338397A (en) * | 1993-10-01 | 1994-08-16 | Motorola, Inc. | Method of forming a semiconductor device |
-
1980
- 1980-12-05 GB GB8039046A patent/GB2089117B/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB2089117A (en) | 1982-06-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19921205 |