GB2087148A

GB2087148A - Composite conductor structure for semiconductor devices

Info

Publication number: GB2087148A
Application number: GB8133069A
Authority: GB
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1980-11-07
Filing date: 1981-11-03
Publication date: 1982-05-19
Also published as: DE3141195C2; HK44686A; IT1140271B; GB2087148B; GB2134706A; DE3141195A1; JPS5780739A; MY8600583A; FR2494042B1; IT8124891A0; GB8331916D0; HK70586A; FR2494042A1; GB2134706B

Abstract

In a semiconductor integrated circuit device the conductive layers forming interconnecting lines are of three- layer construction consisting of a polycrystalline silicon layer (541), a silicide layer (551), of silicon and a refractory metal formed on the polycrystalline silicon layer, and a refractory metal layer (561), formed on the silicide layer. The refractory metal may be molybdenum, titanium tantalum, or tungsten. The polycrystalline layer is formed by a CVD method, the silicon and refractory metal layer is formed by a co-sputtering method, and the refractory metal layer is formed by sputtering. The gates (542, 552, 562) of MISFETs present in the integrated circuit are made in the same way and of the same materials as the interconnecting lines. A dynamic RAM using such a three layer construction for word lines is described. <IMAGE>

Description

SPECIFICATION Semiconductor devices and a process for producing the same Background of the invention The present invention relates to semiconductor integrated circuit devices and a process for producing the same.

In semiconductor integrated circuit devices, and particularly in semiconductor integrated circuit devices containing a pluraity of metal oxide film semi-conductor-type field effect transistors (hereinafter referred to as MISFET's), the wiring layer has often been madeof polycrystalline silicon which has resistance against heat and self-aligning properties, instead of aluminum. The polycrystalline silicon is doped with impurities in order to reduce its very great resistivity. Even after doping with impurities, however, the polycrystalline silicon still exhibits great resistivity compared with aluminum. In the semiconductor integrated circuit devices employing polycrystalline silicon as a wiring layer, therefore, the defect is that the signals are transmitted at slow speeds.

In order to preclude the above-mentioned defect, therefore, it has been known to use a refractory metal such as molybdenum, tungsten, platinum, or tantalum as a material for forming wiring layers (Japanese Patent Laid-Open No. 80986/1978). When a refractory metal is used in pure form as a material for forming wiring layers in the semiconductor integrated circuit device, the device will exhibit small resistivity and increased resistance against the heat treatment, but will present defects such as poor adhesiveness of the layer to the Six2 film or Si3N4 film.

Therefore, it has been attempted to use a silicide layer composed of silicon and a refractory metal as a wiring layer for the semiconductor integrated circuit devices (Japanese Patent Laid-Open No. 80986/ 1978). This wiring layer, however, cannot be intimately adhered onto the SiO2film, and does not provide good contacting property to the silicon substrate, either.

In order to eliminate the above-mentioned defects, furthermore, an attempt has been made to use a wiring layer with double-layer construction consisting of a polycrystalline silicon layer and a silicide layer of silicon and a refractory metal formed on the polycrystalline silicon layer (Japanese Patent Laid Open No.88783/1979). Here, however, the wiring layer with the double-layer construction has a resistivity which is considerably greater than that of a pure refractory metal though it varies depending upon the silicon content in the silicide layer. For example, when molybdenum is used as the refractory metal, the wiring layer consisting of a polycrystalline silicon layer and a silicide layer of silicon and molybdenum formed on the polycrystalline silicon layer, exhibits a resistivity of 100 to 150 1 o-6 ohms.

cm in contrast with the resistivity of pure molybdenum of about 15 x 10.6 ohms.cm.

Summary of the invention The present invention consists in the use of a three-layer construction comprising a polycrystalline silicon layer, a silicide layer which consists of silicon and a refractory metal and which is formed on said polycrystalline silicon layer, and a refractory metal layer formed on said silicide layer.

One aspect of the present invention provides a semiconductor device comprising a semiconductor substrate, an insulating film formed on one main surface of said semiconductor substrate, and a conductive layer selectively formed on said insulating film, said conductive layer being composed of a polycrystalline silicon layer, a silicide layer which consists of silicon and a refractory metal and which is formed on said polycrystalline silicon layer, and a refractory metal layer formed on said silicide layer.

Brief description of the drawings Figure 1 is a section of a semiconductor integrated circuit device according to an embodiment of the present invention; Figure 2 is a circuit diagram of a D-RAM according to the present invention; Figure 3 is a diagram of the lay-out pattern of a D-RAM IC of the two-mat system according to the present invention; Figure 4 is a perspective sectional view showing the construction of memory cell elements according to the present invention; Figure 5 is a perspective sectional view showing the construction of dummy cell elements according to the present invention; Figure 6 is a perspective sectional view showing a portion of the elements in an active restore circuit according to the present invention; Figure 7 is a diagram of the lay-out pattern of a memory array and a dummy array according to the present invention;; Figure 8 is a plan view showing a portion of a semiconductor substrate which illustrates the state of a field insulation film according to the present invention; Figure 9 is a plan view showing a portion of a semiconductor substrate which illustrates the state of a first conductor layer according to the present invention; Figure 10 is a plan view of a semiconductor integrated circuit device which constitutes the active restore circuit according to the present invention; and Figure 11A to 11S are sectional views of the semiconductor integrated circuit device in each of the steps for producing the D-RAM according to the present invention.

Description of the preferred embodiments The invention will be described below with referpence to an embodiment.

Figure 1 is a section view of an MlS4ype semiconductor integrated circuit device according to an embodiment of the present invention, in which reference numeral 51 denotes a p-type silicon substrate, and 52 denotes a field insulating film which is selectively formed by thermal oxidation. An MISFET is formed in a region surrounded by the field insulating film 52.The MISFET consists of a gate insulating film 53 formed by surface oxidation; a gate electrode of a three-layer construction which is made up of a polycrystalline silicon layer 542, a silicide layer (hereinafter referred to as molybdenum silicide layer) 552 of silicon and molybdenum, and a pure molybdenum layer 562; and an N±type semiconductor region 572 which is formed using the gate electrode as a mask and which serves as a selfaligned source region or a drain region; and an N±type semiconductor region 573.

The N±type semiconductor region 572 is connected to other MISFET's through a wiring layer of a three-layer construction consisting of a polycrystalline silicon layer 541, a silicide layer (hereinafter referred to as molybdenum silicide layer 551) of silicone and molybdenum, and a pure molybdenum layer 561, which is in direct contact with an N±type semiconductor region 571 that is continuous with the N±type semiconductor region 572. Further, the N±type semiconductor region 573 is connected to other MISFET's through an aluminum layer 60.

The above gate electrode works not simply as a gate for the MISFET but also as a wiring layer for connecting the gate electrode to, for example, the gates Of other MISFET's in the semiconductor integrated circuit device.

As mentioned already, the time required for transmitting the signals through the wiring layer in the semiconductor integrated circuit should be as short as possible and, for this purpose,theresistivity should be as small as possible. In a dynamic random access memory, in particular, it is desired to reduce the resistivity of the wiring layer as far as possible to increase the speed of transmission of the signals.

The wiring layer of the three-layer construction consisting of a polycrystalline silicon layer, a molybdenum silicide layer and a pure molybdenum layer, exhibits a resistivity of about 30 to 35 microohms.cm. This is about twice that of pure molybdenum which has a resistivity of about 15 microohms.cm, and is about one-fifth to one-third that of the conventional wiring layer which wholly or partly consists of a refractory metal.

The reason why such a small resistivity can be realized is attributed to the presence of the layer of pure molybdenum which forms the uppermost layer of the wiring layer. According to the study conducted by the inventors of the present invention, it was clarified that even when a heat treatment is performed during or after the wiring layer is formed, the three layers constituting the wiring layer do not react among themselves, but retain their properties.

Moreover, the polycrystalline silicon layer which forms the lowermost layer of the wiring layer adheres intimately to an insulating film such as SiO2 film, Si3N4film, or the like, and also comes into ohmic contact with the silicon substrate.

The wiring layer of the three-layer construction of the present invention shown in Figure 1, can be obtained as mentioned below. The polycrystalline silicon layers 541,542 is formed over the whole surface by the vapor-phase chemical reaction method (CVD method) to a thickness of about 1500 to 2500 angstroms, and is doped with phosphorus ions to a high concentration to reduce the resistivity.

Thereafter, molybdenum silicide layer 551, 552 if formed over the whole surface of the polycrystalline silicon layer by, for example, co-sputtering to a thickness of about 1000 angstroms. The silicon content will be 10 % by weight. Then, pure molybdenum layer 561, 562 is formed on the whole surface of the molybdenum silicide layer by, for example, the sputtering method to a thickness of about 1500 angstroms. Using CF4+O2 gas, the above-mentioned layers are continuously subjected to plasma etching to form a wiring layer of the three-layer construction having a predetermined shape as shown in Figure 1.

Thereafter, the wiring layer is annealed in a nitrogen atmosphere such that the uppermost molybdenum layers 561, 562 will not be oxidized or sublimated. The annealing is effected in order that silicon is uniformly dispersed in the molybdenum layers 551, 552 which contain silicon.

In performing the annealing, it was found that the above-mentioned three layers cease to exist if the silicon is contained in a stoichiometric amount, i.e., when the silicon content is 37 % by weight. Namely, when the silicon is contained in a stoichiometric amount, the individual layers undergo chemical reaction, and the stress resulting from the contraction of volume causes the individual layers to be peeled off from each other.

With the present method, however, the abovementioned three layers are bonded to each other, and the resistivity of the wiring layer can be reduced to a value as small as 30 to 35 microohms.cm.

Furthermore, the following effects can be obtained: (1) It is possible to prevent the formation of SiO2 film on the interface between the polycrystalline silicon layers 541,542 and the molybdenum silicide layers 551,552. The molybdenum silicide layers 551,552 are formed by co-sputtering. In this case, oxygen in the atmosphere is taken into the molybdenum silicide layers 551,552. Prior to reacting with silicon in the polycrystalline silicon layers 541, 542, the oxygen reacts with silicon contained in the molybdenum silicide layers 551,552 to form SiO2. Therefore, no SiO2 film is formed on the interface. Further, since silicon is present in an isolated manner in the molybdenum silicide layers 551, 552, the SiO2 film is not formed in a continuous manner.Further, the oxygen in the atmosphere is taken into the molybdenum layers 561, 562 when they are being formed by the sputtering. The oxygen reacts with silicon in the molybdenum silicide layers 551,552. However, since silicon is present in an isolated manner, oxide film is not formed continuously on the interface.

Since no oxide film is formed on the interface, the resistivity of the wiring layer does not increase.

It was found through the study conducted by the inventors of the present invention that a substance that serves as an oxygen getter should be contained in the second layer so that oxygen taken from the atmosphere will not form an oxide film on the interface. It was confirmed that such a substance needs be contained in an amount of 5 % by weight to 10 % by weight. The substance which serves as an oxygen getter should be determined by taking into consideration the chemical relation to the three layers forming the wiring layer, i.e., by taking into consideration the adhesiveness and the chemical reaction that may take place during the step of heat treatment.

(2) When the wiring layer consisting of the polycrystalline silicon layer 541, the molybdenum silicide layer 551 formed thereon, and the molybdenum layer 561, is brought into direct contact with the semiconductor region to form an electrode, the resulting ohmic contact obviates the need for form ing a high-concentration region. This is due to the fact that impurities doped in the polycrystalline silicon are diffused into the semiconductor region to form a high-concentration region.

(3) Impurities are taken from the atmosphere into the molybdenum silicide layers 551, 552 when they are formed by the co-sputtering. However, since there exists a polycrystalline silicon layer therebetween, impurities such as sodium ions are not diffused into the activated semiconductor region.

As described above, therefore, it is possible to obtain a semiconductor integrated circuit device having a small resistivity and a short signal transmission time.

The invention will be described below by way of concrete embodiments. In the below-mentioned embodiments, the present invention is adapted to a dynamic random access memory (hereinafter referred to as D-RAM).

First, the setup of the D-RAM circuit is briefly mentioned below with reference to Figure 2.

The D-RAM circuit consists of an address buffer ADB for introducing address signals Ao - Aj, a row and column decoder RC-DCR for selecting a given row address line and a given column address line from the row address signals Ao - A and the column address signals Aj+1 - Aj, a memory array M-ARY having a plurality of memory cells M-CEL's, a dummy array D-ARY having a plurality of dummy cells D-CEL's, a column switch C-SW1 for selecting any data line in the M-ARY responsive to a selected column address signal, a sense amplifier SA, a data input buffer DIB, an output amplifier OA, and a data output buffer DOB.

The M-CEL consists of a capacitor C5 for storing the data and an MISFET QM for selecting the address, and the data "1" or "0" is stored in the form of whether there is electric charge in the capacitor C5 or not.

The D-RAM circuit is arrayed on a single semiconductor chip as concretely shown in Figure 3.

Figure 3 is a diagram of lay-out pattern of the D-RAM IC of a so-called two-mat system in which the memory array is divided into two in a single semiconductor chip.

First, the two memory arrays M-ARY1 and M-ARY2 consisting of a plurality of memory cells are placed in an IC chip, separated away from each other.

A common column decoder C-DCR is arrayed on the central portion of the IC chip between M-ARY1 and M-ARY2.

The column switch C-SW1 for the M-ARY1 and the dummy array D-ARY1 consisting of a plurality of dummy cells are placed between M-ARY1 and C DCR.

On the other hand, the column switch C-SW2 for the M-ARY2 and the dummy array D-ARY2 consisting of a plurality of dummy cells are placed between M-ARY2 and C-DCR.

The sense amplifiers SA1 and SA2 are located at an extreme left portion and at an extreme right portion of the IC chip, so that they will not be erroneously operated by noise such as signals applied to the C-DCR, and so that the wiring can be easily laid out.

On the upper left side of the IC chip are arrayed a data input buffer DIB, a read and write control signal generator R/W-SG, a RAS signal generator RAS-SG, and a RAS family signal generator SG. Adjacent to these circuits, there are further arrayed a RAS signal applying pad P-RAS, a WE signal applying pad P-WE, and a data signal applying pad P-Di,.

On the upper right side of the IC chip, on the other hand, there are arrayed a data output buffer DOB, a CAS signal generator CAS-SG, and a CAS family signal generator SG2. Adjacent to these circuits, there are arrayed a V55 voltage supplying pad P-Vss, a CAS signal applying pad P-CAS, a data signal output pad P-Dout, and an address signal A6 supplying pad P-A6.

A main amplifier MA is placed between the RAS family signal generator SG1 and the CAS family signal generator SG2.

A V66 generator VBB-G is located above a circuit which occupies large areas such as RAS family signal generator SG1, CAS family signal generator SG2 or main amplifier MA. This is because, the V56-G produces a minority carrier, and the data in the memory cells constituting the M-ARY1 and M-ARY2 may be undesirably inverted by the minority carriers. In order to prevent such a probability, therefore, the VBB generator V66-G is located at a position remote from the M-ARY1 and M-ARY2.

The row decoder R-DCR1 for the M-ARY1 is located on the lower left side of the IC chip. Adjacent to the R-DCR1, there are arrayed address signal supplying pads P-Ao, P-A1, P-A2, and a Vcc voltage supplying pad p-VCc.

On the lower right side of the IC chip, on the other hand, there is provided a row decoder R-DCR2 for the M-ARY2. Adjacent to the raw decoder R-DCR2, there are arrayed address signal applying pads P-A3, P-A4, P-A5, and P-A7.

An address bufferADB is disposed between R-DCRn and R-DCR2.

The D-RAM: IC has a capacity of about 64 kilobits divided into two memory cell matrixes (memory arrays M-ARY1 and M-ARY2) each having a memory capacity of 128 rows x 256 columns = 32,768 bits (32 kilobits). Therefore, one memory array has 128 word lines WL and 256 data lines DL.

The above data lines DL are made of aluminum and have a small resistivity. Further, as will be obvious from Figure 3, the data lines DL are short and impose no problem with regard to the time for transmitting the signals applied by the column decoder C-DCR to each of the memory cells.

On the other hand, as will be understood from Figure 3, the word lines WL are much longer than the data lines DL. If the word lines WL have large resistivities, extended periods of time are needed to transmit the signals applied by the row decoder R-DCR to each of the memory cells, particularly to transmit the signals applied by the row decoder R-DCR to the memory cells located at the most remote positions.

The signal transmission time of the word lines WL determines the operation time of the D-RAM, and eventually determines the operation time of the whole D-RAM system.

According to the embodiment of the present invention, the word lines WL consist of a polycrystalline silicon layer, a molybdenum silicide layer formed thereon, and a pure molybdenum layer formed further thereon, as shown in Figure 1. The word lines have a resistivity of 30 to 35 microohms.cm which is one-fifth to one-third that of the conventional word lines. According to the embodiment of the present invention, therefore, the D-RAM permits the signals to transmit in less time than the conventional D-RAM, and operates at speeds faster than the conventional D-RAM. Further, the whole D-RAM system can be operated at high speeds.

According to the embodiment of the present invention, furthermore, not only the word lines but also the gate electrodes of all MISFET's in the D-RAM are formed in the three-layer contruction. According- ly, the D-RAM operates at higher speeds.

Construction of the principal elements and lay-out pattern in the embodiment of the present invention will be discussed below in further detail.

[Construction of memory cell M-CEL] Figure 4 is a perspective section view showing the construction of a memory cell M-CEL of Figure 2, in which reference numeral 1 denotes a p-type semiconductor substrate, 2 denotes a relatively thick insulating film (hereinafter referred to as field insult ing film), 3 denotes a relatively thin insulating film (hereinafter referred to as gate insulating film), 4 and 5 5 denote N±type semiconductor regions, 6 denotes a first polycrystalline silicon layer, 7 denotes an n-type surface inverter layer, 8 denotes a second polycrystalline silicon layer, 9 denotes a PSG (phos phorus silicate glass) layer, 10 denotes an aluminum layer, 29 denotes a molybdenum silicate layer, and 36 denotes a molybdenum layer.

A MISFET QM in a memory cell M-CEL has a substrate, a source region, a drain region, a gate insulating film and a gate electrode, that are, respectively, made up of the above-mentioned p-type semiconductor substrate 1, the n±type semiconductor region 4, the n±type semiconductor region 5, the gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 8, a a molybdenum silicide layer 29, and a molybdenum layer 36. The multi-layer electrode can be used, for example, as a word line WL1.2 which is shown in Figure 2. The aluminum layer 10 connected to the n±type semiconductor region 5 is used, for exam ple, as a data line DLa 1 which is shown in Figure 2.

On the other hand, a memory capacitor Cs in the memory cell M-CEL has an electrode, a dielectric layer and another electrode which are, respectively, made up of a first polycrystalline silicon layer 6, a gate insulating film 3, and an n-type surface inverted layer 7. Namely, the power-supply voltage Vcc applied to the first polycrystalline silicon layer 6 induces the n-type surface inverter layer 7 on the surface of the p-type semiconductor substrate 1 through the gate insulating film 3 owing to the effect of the electric field.

[Construction of dummy cell D-CEL] Figure 5 is a perspective section view showing the construction of a dummy cell D-CEL which is illustrated in Figure 2. In Figure 5, reference numerals 11 to 14 denote n±type semiconductor regions, 15 denotes a first polycrystalline silicon layer, 16 denotes an n-type surface inverter layer, 17 and 18 denote second polycrystalline silicon layers, 19 denotes an aluminum layer, 30 and 31 denote molybdenum silicide layers, and 37 and 38 denote molybdenum layers.

A MISFET QD1 in a dummy cell D-CEL has a substrate, a drain region, a source region, a gate insulation film and a gate electrode, which are, respectively, made up of the p-type semiconductor substrate, an n±type semiconductor region 11, an n ±type semiconductor region 12, a gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 17, a molybdenum silicide layer 30 and a molybdenum layer 37.

The multi-layer electrode stretches on the p-type semiconductor substrate 1 as a dummy word line DWL1.2 which is shown in Figure 2. The aluminum layer 19 connected to the n±type semiconductor region stretches on the p-type semiconductor substrate 1 as a dummy data line DL1.1 shown in Figure 2.

A MISFET QD2 in the dummy cell D-CEL has a substrate, a drain region, a source region, a gate insulating film and a gate electrode, that are, respectively, made up of the p-type semiconductor substrate 1, an n±type semiconductor region 13, an n±type semiconductor region 14, a gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 18, a molybdenum silicide layer 31 and a molybdenum layer 38.

The multi-layer electrode is served with a discharge signal Plde which is diagrammed in the dummy cell D-CEL of Figure 2.

The capacitor Cds in the dummy cell D-CEL has one electrode, a dielectric layer and another electrode, that are, respectively, made up of a first polycrystalline silicon layer 15, a gate insulating film 3 and an n-type surface inverted layer 16. Namely, the power supply-voltage Vcc applied to the first polycrystalline silicon layer 15 induces the n-type surface inverted layer 16 on the surface of the p-type semiconductor substrate 1 via the gate insulating film 3 owing to the effect of the electric field.

[ Construction of a portion of a peripheral circuit (active restore ARI) ] Figure 6 is a perspective section view showing the construction of a portion of the peripheral circuit formed in the periphery of the memory array M-ARY, i.e., showing a portion of the active restore AR1 which is shown in Figure 2. In Figure 6, reference numerals 20 to 23 denote n±type semiconductor regions, 24 to 27 denote second polycrystalline silicon layers, and 28 denotes an aluminum layer.

Reference numerals 32 to 35 denote molybdenum silicide layers, and 39 to 42 denote molybdenum layers.

A MISFET Q56 in the active restore AR1 shown in Figure 2 has a substrate, a source region, a drain region, a gate insulating film and a gate electrode, that are, respectively, made up of a p-type semiconductor substrate 1, an n±type semiconductor region 20, an n±type semiconductor region 21, a gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 24, a molybdenum silicide layer 32 and a molybdenum layer 39.

A MISFET Q54 in the active restore AR1 has a substrate, a source region, a drain region, a gate insulating film and a gate electrode, that are, respectively, made up of a p-type semiconductor substrate 1, n n±type semiconductor region 22, an n±type semiconductor region 23, a gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 27, a molybdenum silicide layer 35 and a molybdenum layer 42. The multi-layer electrode is served with an active restore control signal ~rg which is shown in Figure 2.

A capacitor Cell in the active restore AR1 has a dielectric layer and an electrode that are, respectively, made up of the gate insulating film 3 and a multi-layer electrode consisting of a second polycrystalline silicon layer 25, a molybdenum silicide layer 33 and a molybdenum layer 40. The multi-layer electrode is connected to a multi-layer electrode which serves as a gate electrode of the MlSFETQs6 and which consists of a second polycrystalline silicon layer 24, a molybdenum silicide layer 32 and a molybdenum layer 39.Further, a portion 25a of the second polycrystalline silicon layer 25 is directly connected to the n±type semiconductor region 22 of the MISFETOs4. This is because, if the molybdenum layer 40 and the n±type semiconductor region 22 are connected together via an aluminum wiring layer, a contact area must be formed between the molybdenum layer 40 and the aluminum wiring layer and makes it difficult to increase the wiring density. Therefore, the above-mentioned connection means is employed to increase the wiring density.

Another electrode of the capacitor CB11 consists of an inverter layer which is formed on the surface of the semiconductor substrate 1. The inverted layer is established by a voltage which is applied to the multi-layer electrode consisting of the second polycrystalline silicon layer 25, a molybdenum silicide layer 33 and a molybdenum layer 40. Although not diagrammed in Figure 6, the inverted layer is contiguous with the n±type semiconductor region which is formed in the semiconductor substrate 1 and which is served with an active restore control signal ~rs of Figure 2. Further, as an electrode of the capacitorC811,there may exist a molybdenum silicide layer and a molybdenum layer on the polycrystalline silicon layer.

The multi-layer electrode consisting of a second polycrystalline silicon layer 26, a molybdenum silicide layer 34 and a molybdenum layer 41, serves as one electrode of the capacitor C812 which is shown in Figure 2, and a portion thereof is directly connected to the source region of the MISFETO56 of Figure 2 like the capacitor Cub11, and another portion thereof is connected to the gate electrode of the MlSFETQ57.

[Lay-out patterns of memory array M-ART and dummy array D-ARY ] Lay-out patterns of the aforementioned memory array M-ARY and the dummy array D-ARY are described below with reference to Figure 7.

The memory array M-ARY shown in Figure 7 has a plurality of memory cells M-CEL shown in Figure 4, which are arrayed on the semiconductor substrate 1.

On the other hand, the dummy array D-ARY shown in Figure 7A has a plurality of dummy cells D-CEL of Figure 5, which are arrayed on the semiconductor substrate 1.

First, the memory array M-ARY shown in Figure 7 is constructed as mentioned below.

The field insulating film 2 is formed describing a pattern as shown in Figure 8 in order to separate a plurality of memory cells M-CEL which are composed of MISFETs QM and memory capacitors C5 on the surface of the semiconductor substrate 1.

Exceptionally, however, in the present embodiment a field insulating film 2a is formed beneath the contact holes CHo through which the power-supply voltage Vcc is applied to the first polycrystalline silicon layer 6. This is different from the general rule of such layouts. Therefore, no aluminium-silicon alloy formed by the reaction between the aluminum layer and the polycrystalline silicon layer in the vicinity of the contact holes CHo is allowed to penetrate through the insulation film beneath the contact holes CHo, and is prevented from reaching the surface of the semiconductor substrate 1.

The first polycrystalline silicon layer 6 which serves as one electrode of the memory capacitor C5 in the memory cells M-CEL is formed on the field insulating film 2 and on the gate insulating film 3 describing a pattern as shown in Figure 9.

Further, word lines WL1.1 composed of multi-layer wiring of the second polycrystalline silicon layer 8, the molybdenum silicide layer 29 and the molybdenum layer 36 of Figure 4, stretch on the first polycrystalline silicon layer 6 in the vertical direction in Figure 7.

A A power-supply line Vcc-L runs in the lateral direction of Figure 7 to supply power-supply voltage Vcc through the contact hole CHo to the polycrystalline silicon layer 6 which serves as one electrode of the memory capacitor C5.

On the other hand, data lines DL1,, DL1#1 composed of the aluminum layer 10 of Figure 4 run nearly in parallel with the power-supply line Vcc-L as shown in Figure 7. The data line DL,1 is connected to the drain region of MISFET OM in the memory cell M-CEL via a contact hole CHX, and the data line DL, is connected to the drain region of MISFET QM in another memory cell M-CEL via a contact hole CH2.

Further, the data lines DL, 2 DL 2 run in the lateral direction in Figure 7 like the data lines DL1#1 and DL1.1, and are connected to the drain regions of the MlSFETs QM in the memory cells M-CEL at predetermined portions through contact holes.

Next, the dummy cells D-CEL shown in Figure 7 are constructed as mentioned below.

The field insulating film 2 is formed on a portion of the surface of the semiconductor substrate 1, and the gate insulating film 3 is formed on another portion on the surface of the semiconductor substrate 1.

The first polycrystalline silicon layers 1 Sa, 1 Sb run on the field insulating film 2 and the gate insulating film 3 in the vertical direction of Figure 7 being separated away from each other. The widths of the first polycrystalline silicon layers 1 Sa, 1 Sb are very important from the standpoint of determining the capacity of capacitor Cds in the dummy cell D-CEL.

The n±type semiconductor region 14 is positioned between the first polycrystalline silicon layers 15a and the first polycrystalline silicon layer 15b. The n±type semiconductor region 14 is used as a common earth line for a plurality of dummy cells D-CEL.

Further, a dummy word line OWL1.1 composed of a multi-layer wiring of the secondary polycrystalline silicon layer 17, the molybdenum silicide layer 30 and the molybdenum layer 37 of Figure 5, runs on the first polycrystalline silicon layer 15a. The dummy word line DWL1.1 constitutes a gate electrode of MISFET QD1 in the dummy cell D-CEL.On the other hand, a control signal line #dc-L1 of a multi-layer wiring composed of the second polycrystalline silicon layer 18, the molybdenum silicide layer 31 and the molybdenum layer 38 of Figure 5, runs in parallel with the dummy word line DWL1#1 being separated away therefrom, so that the discharge control signal ~dz shown in Figure 5A can be applied. The control signal line ~d-L2 forms a gate electrode of MISFET Q02 in the dummy cell D-CEL.

Similarly, a dummy word line DWL1#2 and a control signal line #dc-L2 run in parallel with the dummy word line DWL1#1 and the control signal line P(daL1~ Further, the data lines DL1~1 DL1#1, DLa DL1.2 composed of aluminum layer stretch from the memory array M-ARY as shown in Figure 7. The data line DL1#1 is connected to the drain region of MISFETQD, in the dummy cell D-CELvia a contact hole CH3, and the data line DL, 2 is also connected to the drain region of MISFET QD1 of another dummy cell D-CELthrough a contact hole CH4.

[ Lay-out pattern of peripheral circuits ] Figure 10 shows a lay-out pattern of a portion of the peripheral circuits, for example, a portion of the sense amplifier SA, of Figure 2.

In Figure 10, AR denotes an active restore portion, and PC denotes a circuit for precharging the data lines.

Two active restores AR1 shown in Figure 2 are provided in the active restore portion AR. Namely, one active restore is formed on the side of arrow A in Figure 10, and another active restore is formed on the side of arrow B. An active restore control signal line pl,,-L consisting of a polycrystalline silicon layer, a molybdenum silicide layer and a pure molybdenum layer, a line ~rs-L consisting of an aluminum layer, and a power-supply line Vcc-L consisting of an aluminum layer, are arrayed in common for the active restores in the active restore portion AR as shown in Figure 10.

On the other hand, the precharging circuit PC contains a circuit for precharging the two data lines that correspond to the two active restores. In the precharging circuit PC are arrayed a potential line V0p-Lcomposed of an aluminum layer, a precharge control signal line ~PC-L, and data lines DL1~1, DLa 1, DLa 2, DLI-2 composed of an aluminum layer which run on the memory array M-ARY of Figure 2, as shown in Figure 10.

MISFETs Qsa to Q57 and capacitors Cub11, CB12 of Figure 2 are arrayed as shown in Figure 10.

Next, a process for producing an n-channel D-RAM will be described below with reference to Figures 11 A to 11 S. In each of the drawings, X1 stands for a section view of the memory array M-ARY of Figure 7 along X1-X1, X2 stands for a section view of the active restore AR of Figure 10 along X2-X2, and X3 stands for a section view of the active restore AR of Figure 10 along X3-X3.

(Step for forming an oxide film and an oxidationresistant film) As shown in Figure 11A, an oxide film 102 and an insulating film, i.e., an oxidation-resistant film 103 which does not permit the passage of oxygen, are formed on the surface of a semiconductor substrate 101.

A A p-type single crystalline silicon (Si) substrate having a crystalline plane (100), a silicon dioxide (SiO2) film and a silicon nitride (Si3N4) film are preferably used for forming the semiconductor substrate 101, the oxide film 102 and the oxidation resistant film 103.

The So02 film 102 is formed by the surface oxidation of the silicon substrate 101 to a thickness of about 500 angstroms, because of the reasons mentioned below. That is, when the Si3N4film 103 is formed directly on the surface of the silicon substrate 101, the surface of the silicon substrate 101 tends to be thermally distorted due to the difference in the thermal expansion coefficient between the silicon substrate 101 and the Si3N4film 103. Consequently, crystalline defect is given to the surface of the silicon substrate 101. In order to prevent this defect, the S~ 2 film 102 is formed on the surface of the silicon substrate 101 prior to forming the Si3N4 film 103.

On the other hand, the Si3N4 film 103 which will be used as a mask for selective oxidation of the silicon substrate 101, is formed to a thickness of about 1400 angstroms by the CVD (chemical vapor deposition) method, as will be mentioned later in detil.

(Step for selectively removing oxidation-resistant film and for injecting ions) A photoresistfilm 104 which serves as an etching mask is selectively formed on the surface of the Si3N4 film 103 that is to be selectively removed from the surface of the silicon substrate 101 on which will be formed a relatively thick insulating film, i.e., a field insulating film. Under this condition, the exposed portions of the Si3N4 film 103 are removed by the plasma etching method which features good etching precision.

Then, impurities of the same type of conductivity as the substrate 101, i.e., p-type impurities are introduced into the silicon substrate 101 through the SiO2 film 102 that is exposed at portions which are not covered with the photoresist film 104 as shown in Figure 11B,sothataso-called inverted layer of the type of conductivity opposite to that of the substrate will not be formed on the surface of the substrate 101 on which the field insulating film is formed. The p-type impurities can be introduced preferably by the ion-injection method. For example, boron ions which are p-type impurities can be injected into the silicon substrate 101 at an injection energy of 75 KeV. In this case, the dosage of ions will be 3 x 1012 atoms/cm2.

(Step for forming field insulating film) Afield insulating film 105 is selectively formed on the surface of the silicon substrate 101. Namely, after the photoresist film 104 is removed, the surface of the silicon substrate 101 is selectively oxidized by thermal oxidation using the Si3N4 film 103 as a mask, to form the Sip film 105 (hereinafter referred to as a field SiO2 film) of a thickness of about 9500 angstroms, as shown in Figure 11 C. When the field SiO2 film 105 is being formed, the injected boron ions diffuse into the silicon substrate 101, thereby to form a p-type inversion preventing layer (not shown) of a predetermined depth beneath the field SiO2 film 105.

(Step for removing oxidation-resistant film and oxide film) The Si3N4 film 103 is removed using, for example, a hot phosphoric acid (H3PO4) solution in order to expose the surface of the silicon substrate 101 of the portions where the field SiO2 film 105 is not formed.

Then, the SiO2 film is removed by using a hydrofluoric acid (HF) solution, so that the surface of the silicon substrate 101 is selectively exposed as shown in Figure 11D.

(Step for forming a first gate insulating film) Afirst gate insulating film 106 is formed on the exposed surfaces of the silicon substrate 101 as shown in Figure 11 E in order to form a dielectric layer for the capacitors Cs, Dds in the memory cells M-CEL and in the dummy cells D-CEL. Namely, the surface of the exposed silicon substrate 101 is thermally oxidized to form the first gate insulating film 106 having a thickness of about 430 angstroms on the surface of the silicon substrate 101. Therefore, the first gate insulating film 106 consists of SiO2.

(Step for adhering a first conductor layer) A first conductor layer 107 is formed on the whole surface of the silicon substrate 101 as shown in Figure 11 F so that it can be used as one electrode of capacitors in the memory cells and in the dummy cells. Namely, a polycrystalline silicon layer 107 which serves as the first conductor layer is formed on the whole surface of the silicon substrate 101 by the CVD method. The polycrystalline silicon layer 107 has a thickness of about 4000 angstroms. Then, in order to reduce the resistance of the polycrystalline silicon layer 107, n-type impurities, such as phosphorus ions, are introduced into the polycrystalline silicon layer 107 by the diffusion method.

Therefore, the polycrystalline silicon layer 107 possesses a resistivity of about 16 ohms/cm2.

(Step for selectively removing the first conductor layer) In order to form the first conductor layer, i.e., the first polycrystalline silicon layer 107 into electrodes of a predetermined shape, the first polycrystalline silicon layer 107 is selectively removed by the photoetching method as shown in Figure 11 G, thereby to form electrodes 108. The first polycrystalline silicon layer 107 can be selectively removed by plasma etching which features good etching precision. Therefore, the exposed first SlO2 gate film 106 is subjected to etching, so that surfaces of the silicon substrate 101 are partially exposed.

(Step for forming a second gate insulating film) A second gate insulating film 109 is formed on the exposed surface of the silicon substrate 101 as shown in Figure 11 H in order to obtain a gate insulating film for the MISFET's in the memory cells M-CEL, dummy cells D-CEL, and in the peripheral circuits. Namely, the exposed surface of the silicon substrate 101 is thermally oxidized to form a second gate insulating film 109 of a thickness of about 530 angstroms on the surface of the silicon substrate 101. Therefore, the second gate insulating film 109 consists of SiO2.The surface of the electrodes 108 composed of the first polycrystalline silicon is also oxidized simultaneously with the formation of the second gate insulating film, i.e., simultaneously with the formation of the second SlO2 gate film 109; an SiO2 film 110 having a thickness of about 2200 angstroms is formed on the surface of the electrodes 108. The Sip film 110 serves as an insulating layer between the electrodes 108 and the electrodes composed of a second polycrystalline silicon that will be mentioned later.

(Step for injection ions for controlling low threshold voltage) P-type impurities are introduced into the surface of the substrate through the second SiO2 gate film 109 by the ion-injection method as shown in Figure III in order to define a threshold voltage of MISFETs Qsi to 053,056 and 057 which are shown in Figure 2 and which have a low threshold voltage. Boron ions will be used as the p-type impurities. The energy for injection will be 75 KeV, and the dosage of ions will preferably be 2.4 x 1011 atoms/cm2.

In this case, ions are injected without using a selection mask. Therefore, boron ions are also introduced into the surfaces of the substrate where other MISFET's are to be formed, such as QM, QD1, QD2, QD4, 005.

(Step for injecting ions for controlling high threshold voltage) A mask for ion injection, i.e., a photoresist film 111 is formed on the second SiO2 gate film 109 on the channel region of MISFETOsl to 053, Qse and 057 as shown in Figure 11J, and boron ions are injected under this condition in orderto define a threshold voltage of MISFET's having a threshold voltage greater than that of MISFETs Osl to 053,056 and Qs7 shown in Figure 2, i.e., in order to define a threshold voltage of MISFET QM in the memory cells, MISFETs QD1, OD2 in the dummy cells, and MISFETs 054, Qs5 in the active restores. The injection energy will be 75 KeV, and a preferred dosage of ions will be 1.0 x 1011 atoms/cm2.

Consequently, the impurity concentration is further increased in the surface of the portions of the substrate where MlSFETs 0M QD1, QD2, Qsa and Qss are to be formed. Therefore, these MISFET's have a high threshold value.

(Step for forming holes for direct contact) Holes for directly connecting one electrode 25 of the capacitor CB11 to the n±type semiconductor region 22 of MISFEET Qs4 as mentioned with reference to Figure 6 are formed, i.e., so-called direct contract holes CH1oot are formed by selectively etching the second SiO2 gate film using the photoresistfilm 112 as a mask, as shown in Figure 11K.

(Step for adhering a second conductive layer) A second conductive layer is formed on the whole surface of the silicon substrate 101 so that it can be used as a gate electrode and a wiring layer for all of the MISFET's. Namely, a polycrystalline silicon layer, a a silicide layer of silicon and a refractory metal, and a pure refractory metal layer are formed as a second conductive layer, as shown in Figure 11 L. First, a polycrystalline silicon layer 113 is formed on the whole surface of the silicon substrate 101 by the CVD method (chemical vapor deposition method). The polycrystalline silicon layer 113 has a thickness of about 1500 to 2500 angstroms. Then, n-type impurities such as phosphorus ions are introduced into the polycrystalline silicon layer 113 by the diffusion method, in orderto decrease the resistance.Some of the phosphorus ions are introduced into the silicon substrate 101 through direct contact holes CH100- Therefore, there is no need of forming highconcentration regions for ohmic contact.

Then, a silicide layer 128 of silicon and a refractory metal is formed on the whole surface of the polycrystalline silicon layer 113. Molybdenum will be used as the refractory metal. Molybdenum and silicon are deposited on the polycrystalline silicon layer by the co-sputtering method in order to form a mixed layer of silicon and molybdenum. The silicon content will be, for example, 10 % by weight. The sputtering conditions will consist of a vacuum degree of smaller than 40 #Pa before argon gas is introduced, an argon-gas pressure of 4.0 Pa when the sputtering is being effected, a molybdenum deposition rate of 0.1 to 0.8 nm/sec., and a silicon deposition rate of 0.1 nm/sec or less. The molybdenum silicide layer 128 consisting of silicon and molybdenum has a thickness of about 1000 angstroms.

A pure refractory metal layer 130 is then formed on the whole surface of the molybdenum silicide layer 128. Molybdenum will be used as the refractory metal. The sputtering method is used for forming the refractory metal layer. In this case, the sputtering is effected under the same conditions as above. The molybdenum layer has a thickness of about 1500 angstroms.

(Step for selectively removing the second conductive layer) The second conductive layer, i.e., the second polycrystalline silicon layer 113, molybdenum silicide layer 128 and the molybdenum layer 130 are selectively removed to form predetermined electrodes or wirings by the dry-etching method using a photoresist. A gas consisting, for example, of CF4 + 02 iS used as an etching gas. The above-mentioned three layers are removed by etching (plasma etching) or by plasma discharge in the presence of the gas. First, the molybdenum layer is subjected to the etching, the molybdenum silicide layer is subjected to the etching next, and the polycrystalline silicon layer is subjected to the etching maintaining the same shape in the presence of the same gas.

Then, the annealing is effected in an nitrogen atmosphere. Owing to the annealing, molybdenum and silicon are uniformly dispersed in the molybdenum silicide layer 129. The polycrystalline silicon layer 114, the molybdenum silicide layer 129, and the molybdenum layer 131, that are formed in the shapes as shown in Figure 11 M by the plasma etching, form word lines WL1#1 to WL1#6, dummy word lines DWL1#, DWL1#2, and control signal lines Ibdc-Llr ~d-L2, which are shown in Figue 7, and further form active restore control signal line ~rg-Lt electrode 114 for the capacitors CB11, CB12, and gate electrodes for the MISFETOsl and Qs2, which are shown in Figure 10.In Figure 11 M, furthermore, the exposed second SiO2 gate film 109 is removed, to expose the surface of the silicon substrate 101.

(Step for oxidizing the surface) An SiO2 film 115 of a thickness of about 100 angstroms is formed by the chemical vapor deposition (CVD) method on the surface of the exposed silicon substrate 101, as shown in Figure 11 N, so that the surfaces where source regions and drain regions of MISFET's are to be formed, will not be contaminated.Simultaneously with the formation of the SiO2 film 115, an SiO2film 116 having a thickness of about 100 angstroms is also formed by the CVD method, as shown in Figure 11 N, on the surfaces of word lines WL" toWL18, dummy word lines DWL1.1, DWL12, control signal lines ~dC-L" ~dC-L2, electrode 114 of the capacitors C811, Cub12, and gate electrodes of MIS FETs Osl to 053, which consist of the second polycrystalline silicon layer 113, molybdenum silicide layer 128 and molybdenum layer 130.

In forming the SiO2 films 115 and 116, the following measure is taken in order to prevent the molybdenum layer 114 from being oxidized and sublimated.

First, the semiconductor substrate 101 is set into a device for forming the Si02 film by the CVD method.

In this case, the temperature in the device is lower than 200 C. Then, nitrogen gas is allowed to flow sufficiently so that no oxygen is present in the device. Then, the SiO2 film is formed by elevating the temperature in the device to about 400 to 4500C.

Concretely speaking, SiH4 + O2 is allowed to flow with the nitrogen gas as a carrier gas; the SiH4 +02 gas is thermally decomposed and is reacted. Oxygen introduced at this moment does not react with molybdenum but reacts with silicon to form an SiO2 film on the surface of the substrate.

(Step for forming source and drain regions) N-type impurities such as arsenic ions are introduced into the silicon substrate 101 through the SiO2 film 115, as shown in Figure 110, in order to selectively form source and drain regions of MIS FET's in the silicon substrate 101. The n-type impurities can be introduced preferably by the ion-injection method. For example, arsenic ions are injected into the silicon substrate 101 at an injection energy of 80 KeV. In this case, the dosage of ions will be 1 x 1016 atoms/cm2.

(Step for forming contact holes) Contact holes are formed in the SlO2 film to connect the source and drain regions to the third conductive layer. Namely, contact holes Cm101 to CH104 are formed as shown in Figure 11P by selectively etching the SiO2 film 115 using a predetermined mask. Here, the contact hole CH102 corresponds to the contact hole CH1 of Figure 7.

(Step for forming interlayer insulating film) An interlayer insulating film is formed on the whole surface of the silicon substrate 101. That is, an inter-layer insulating film 118, for example, a phosphorus silicate glass (PSG) film having a thickness of about 8000 angstroms is formed on the whole surface of the silicon substrate 101, as shown in Figure 11Q. The PSG film 118 also serves as a sodium ion getter which affects the characteristics of MISFET's (Step for forming contact holes) Contact holes are formed in the PSG film 118 in order to connect the second polycrystalline silicon layer to the third conductive layer, and the source and drain regions to the third conductive layer. That is, the PSG film 118 is subjected to the selective etching to form contact holes CHno, to CH,04, as shown in Figure 11 R.The mask used for forming the contact holes CHao, to CH104 is the same as the mask used for forming the contact holes CH101 to Cm104 in the aforementioned step for forming contact holes.

Therefore, the PSG film 118 is thermally treated at a temperature of about 1 000#C in order to flatten it.

Arsenic ions injected through the heat treatment are diffused to form n±type semiconductor regions 119 to 126 having a predetermined depth. The n±type semiconductor regions 119 to 126 serve as source and drain regions.

Here, the contact holes formed in the SoO2 film 115 in the aforementioned step, may be formed simultaneously with the formation of contact holes in the PSG film 118. However, the PSG film 118 is subjected to the etching before the contact holes are completely formed in the SiO2 film 115. In other words, the PSG film 118 subjected to over-etching. In order to prevent the over-etching, therefore, the contact holes should be formed in the PSG film 118 through a step different from the step for forming the contact holes in the S;O2 film 115.

(Step for forming a third conductive layer) Athird conductive layer, for example, an aluminum layer having a thickness of about 12000 angstroms is formed on the whole surface of the silicon substrate 101, in order to form the power-supply line Vcc-L, and data lines DL1.1, DL1.1, Do,2, and DL1.2, that are shown in Figure 7. The aluminum layer is then subjected to the selective etching to form a power-supply line Vcc-L, data line DLX 1 and wiring layer 127, as shown in Figure 11 S.

According to the above-mentioned embodiment of the present invention, it is possible to realize a D-RAM IC, i.e., a semiconductor integrated circuit device having a wiring layer of a small resistivity and fast signal transmission speed. Further, the effects (1) to (3) obtained in the first embodiment can also be equally obtained by this embodiment. According to this embodiment, in particular, the first conductive layer consists of polycrystalline silicon. However, since the first conductive layer is always impressed with a predetermined voltage or is grounded, there arises no problem even when it has a high resistivity. Rather, the first conductive layer composed of polycrystalline silicon makes it possible to form a dense insulating film (SiO2film) by thermally oxidizing the surface thereof.

According to the embodiment of the present invention, furthermore, a semiconductor integrated circuit device having the above-mentioned effects can be obtained without passing through complicated manufacturing steps. Namely, according to the embodiment of the present invention, the wiring layer consisting of polycrystalline silicon layer 114, molybdenum silicide layer 129 formed on the layer 114, and molybdenum layer 131 formed on the layer 129, serves as an electrode that comes into direct contact with the n±type semiconductor region 22, serves as a gate electrode for MISFET's, and serves as one electrode of MIS capacitors.When the individual electrodes are to be formed using separate materials, i.e., when the electrode that comes into direct contact with the semiconductor region, gate electrode of MISFET's, and on electrode of MIS capacitors, are to be formed using separate materials, increased number of manufacturing steps will be necessary.

Further, simultaneous formation of one electrode of MIS capacitors and the electrode that comes into contact with the semiconductor region 22, helps increase the degree of integration. That is, if these electrodes are made of different materials, a contact area must be provided between the two electrodes.

Therefore, the above-mentioned manufacturing steps are effective to increase the density of wiring.

The molybdenum silicide layer which serves as one electrode of MIS capacitors presents no problem.

The present invention should in no way be limited to the above-mentioned embodiments only. For example, in addition to using molybdenum silicide (MoSi), it is also allowable to use titanium silicide (TiSi2), tantalum silicide (TaSi) or tungsten silicide (WSi) as a second conductive layerforforming multi-layer wiring.

In addition to molybdenum, furthermore, it is also allowable to use titanium, tantalum or tungsten as a refractory metal.

Furthermore, the steps of Figures 11 L to 110 in the above-mentioned embodiment can be rearranged as mentioned below. First, the polycrystalline silicon layer 113, the silicide layer 128 of silicon and refractory metal, and the pure refractory metal layer 131 are laminated in the order mentioned on the SiO2 gate film 109 and on the SiO2 field film 105, as shown in Figure 11 L. Then, the above-mentioned three layers are selectively removed by dry etching to form a wiring layer or gate electrode. Source and drain regions are then formed beneath the SiO2 gate film 109 using the wiring layer as a mask. These regions are formed by the ion implantation method.

According to the present embodiments, therefore, it is possible to obtain semiconductor integrated circuit devices having a high density which results from the self-matching property, and having a wiring layer with small resistivity and short signal transmission time.

Claims

1. A semiconductor device comprising a semiconductor substrate, an insulating film formed on one main surface of said semiconductor substrate, and a conductive layer selectively formed on said insulating film, said conductive layer being composed of a polycrystalline silicon layer, a silicide layer which consists of silicon and a refractory metal and which is formed on said polycrystalline silicon layer, and a refractory metal layer formed on said silicide layer.

2. A semiconductor device according to claim 1, wherein a portion of said conductive layer serves as a gate electrode, and source and drain regions are formed in the semiconductor substrate one on each side of the gate electrode.

3. A semiconductor device according to claim 1, or claim 2 wherein said conductive layer provides a word line connected to memory cells.

4. A semiconductor device according to any one of the preceding claims, wherein a portion of said conductive layer is connected to one main surface of the exposed semiconductor substrate.

5. A semiconductor device according to any one of the preceding claims, wherein said insulating film consists of a field insulating film having a large thickness, and a gate insulating film thinner than said field insulating film.

6. A semiconductor device according to any one of the preceding claims, wherein said insulating film consists of an SiO2film, and said semiconductor substrate consists of a silicon substrate.

7. A semiconductor device according to any one of the preceding claims, wherein the silicide layer of silicon and a refractory metal is a silicide layer consisting of silicon and molybdenum, and the refractory metal layer formed thereon is a molybdenum layer.

8. A semiconductor device according to any one of claims 1 to 6, wherein the silicide layer of silicon and a refractory metal is a silicide layer consisting of silicon and titanium.

9. A semiconductor device according to any one of claims 1 to 6, wherein the silicide layer of silicon and a refractory metal is a silicide layer consisting of silicon and tantalum.

10. An MlS-type field effect transistor comprising a gate insulating film formed on one main surface of a semiconductor substrate, a gate electrode selectively formed on said gate insulating film, and source and drain regions formed in the semiconductor substrate on both sides of said gate electrode, wherein said gate electrode comprises three layers, i.e., comprises a polycrystalline silicon layer selectivelyformed on said gate insulating film, a silicide layer of silicon and a refractory metal formed on said polycrystalline silicon layer, and a refractory metal layer formed on said silicide layer of silicon and the refractory metal, and said source and drain regions are self-aligned by the gate electrode which consists of said three layers.

11. A semiconductor memory integrated circuit device comprising data lines that run in parallel with each other, word lines that run in a direction generally at right angles to said data lines, and memory cells connected between said data lines and said word lines, wherein said word lines comprise three layers, i.e., comprise a polycrystalline silicon layer, a silicide layer of silicon and a refractory metal formed on said polycrystalline silicon layer, and a refractory metal layer formed on said silicide layer of silicon and the refractory metal.

12. A semiconductor integrated circuit device comprising a semiconductor substrate, an insulating film formed on one main surface of said semiconductor substrate such that said one main surface is selectively exposed, and a conductive layer which is connected to an exposed portion of said one main surface and which extends up to said insulating film, wherein said conductive layer comprises three layers, i.e., comprises polycrystalline silicon layer, a silicide layer of silicon and a refractory metal, and a refractory metal layer, laminated in that order.

13. A process for producing semiconductor devices comprising: a step for forming an insulating film on one main surface of a semiconductor substrate; a step for forming a polycrystalline silicon layer on said insulating film; a step for forming a deposited layer of silicon and a refractory metal by simultaneously sputtering silicon and a refractory metal on said polycrystlline silicon layer; a step for forming a refractory metal layer on the deposited layer of silicon and the refractory metal; and a step for annealing said polycrystalline silicon layer, said deposited layer and said refractory metal layer.

14. A process for producing semiconductor devices according to claim 13, wherein said polycrystalline silicon layer, said deposited layer and said refractory metal layer are subjected to selective etching after they have been formed.

15. A process for producing semiconductor devices by forming an insulating film on one main surface of a semi-conductor substrate, and by selectively forming a gate electrode on the insulating film, wherein said gate electrode is formed by the following procedure: a polycrystalline silicon layer is formed by the CVD method on said insulating film, silicon and refractory metal are deposited on said polycrystalline silicon layer by the co-sputtering method, a refractory metal layer is formed on the deposited layer by sputtering, and the polycrystalline silicon layer, the deposited layer and the refractory metal layer are selectively removed and annealed.

16. A process for producing semiconductor devices according to claim 15, wherein after said gate electrode is formed, a source region and a drain region are formed in the semiconductor substrate one on each side of said gate electrode.

17. A process for producing semiconductor devices according to claim 16, wherein said source and drain regions are formed by the ion implantation method.

18. A process for producing semiconductor devices substantially as any described herein with reference to the accompanying drawings.

19. A semiconductor device substantially as any described herein with reference to the accompanying drawings.

20. A A semiconductor device produced by a process according to any one of claims 13 to 18.