GB2086193A

GB2086193A - Digital Transmission System

Info

Publication number: GB2086193A
Application number: GB8032249A
Authority: GB
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1980-10-07
Filing date: 1980-10-07
Publication date: 1982-05-06
Also published as: GB2086193B

Abstract

In an adaptive equaliser it is desirable to sample the incoming data bits at the right time, and to do this a timing phase control circuit (2) is used. This is controlled from a clock (3), synchronised with the incoming bit streams, and from a coefficient generation circuit (6-7-8). The latter derives a coefficient from each received bit which is subtracted (9) from that bit's value and applied to the circuit (2) to adjust timing. To get rid of inter-symbol interference, similar coefficient generation controlled via a chain of one-circuit delays (10, 11) are used, the coefficients therefore being summated and subtracted from the incoming signals. <IMAGE>

Description

SPECIFICATION Digital Transmission System The present invention relates to an adaptive equaliser for use in a digital transmission system, such as a PCM system.

In a digital transmission system, each bit which is sent, even if it starts out as a well-shaped pulse, is distorted into a curved-sided signal at the receiving end. As the sides of the bit are, in effect, splayed out, it is possible for inter-symbol interference to occur. The purpose of the equaliser to be described herein is to eliminate, or alleviate the effects, of inter-symbol interference using an algorithm which minimises the mean square error between the actual and the desired pulse shapes at the equaliser decision point. The decision time must be synchronous with the transmit symbol rate and also so placed within a symbol period as to maximise the signal-to-noise ratio of the system.

According to the present invention there is provided an adaptive equaliser for equalising received digital data, in which the received data is applied via a sampling circuit to a subtraction circuit whose output is applied to a threshold detector the output of which, digital 1 or O, is the output of the equaliser, in which a number of coefficient generation circuits are provided which generate coefficients dependent on the value of a corresponding number of preceding digital bits, in which a summation circuit summates said coefficients and applies the result of said summation to the other input of the subtraction circuit so that the latter produces an output representing the value of the current sample less interference due to preceding samples, in which a further coefficient generation circuit generates, under the control of the current sample and its output a coefficient whose value is used to adjust the sampling instant within the received symbol period, and in which the output of the subtraction circuit is applied to the threshold detector.

An embodiment of the invention will now be described with reference to the accompanying highly schematic drawings, in which Fig. 1 is an overall block diagram of the system and Fig. 2 shows one implementation of the timing phone control circuit.

The arrangement described herein, Fig. 1, seiects automatically the best sampling instants for the successively-received symbols of a digital input. Specifically it uses a method whereby the timing phase of an adaptive equaliser is automatically adjusted by interrogation of circuit parameters until a predefined criterion is attained, which indicates correct operation. The stochastic algorithm for adjusting the coefficients of an adaptive equaliser for PCM based on minimum mean square error is well-established. For optimum performance the receiver must sample the received symbols (bits) in synchronism with the transmitter symbol rate, and also at the correct phase within each symbol period. A reference clock source synchronised to the transmitted symbol rate is needed, and one way to achieve clock extraction for this purpose is described in our co-pending application no (D.A.Fisher 1). The criterion for correct operation is based on a comparison of the coefficient representing the symbol eye opening and the error estimate generated by the adaptive equaliser for each symbol taken over a number of decisions. This method is described herein for an adaptive decision feedback equaliser (ADFE).

The function of the equaliser is to remove intersymbol interference, caused as already indicated by the fact that a symbol or bit during transmission is "splayed out" so that successive bits are received overlap. This removal is effected at the decision point of the detector by modification of the detection threshold on the basis of the previous decisions values. For each transmitted symbol (i.e. each bit) it is necessary to sample once and to cancel the inter-symbol interference at this time.

Referring now to Fig. 1, the received data signal r(t) is sampled by a sample and hold circuit 1 at the transmitted bit rate, under control of a timing phase control 2, which is driven by a reference synchronised clock 3. The clock signal from this clock 3 can, as already mentioned, be obtained in the way described in our abovementioned application no. (D.A. Fisher 1). The phase of the output of the circuit 2 is so controlled, as will be described later, as to optimise the sampling instant within the bit period.

The output from the sample and hold circuit is applied to the + input of a subtraction circuit 4.

The other input to this circuit 4 is an estimate of the inter-symbol interference, which as will be seen later, is formed by summating the estimated interference due to a number of previouslytransmitted symbols. Each constituent of the sum is formed by the product of the decision value of the nth previous sample and the estimated value of the current time response of the transmission channel due to the nth previous sample. The number of such constituents to be summated to produce the subtrahend for the subtraction circuit depends on the parameter of that channel, i.e. on how far the symbol edges are spread out by the distortion which is inevitably introduced on that channel.

The output from the subtraction circuit 4 is applied to a threshold detector 5 set to pass the received data to the data output.

There is a first coefficient generation circuit which includes a first multiplier 6, an integrator 7 which integrates over a period dependent on loop gain A, and a second multiplier 8. The multiplier 8 feeds the negative input of another subtraction circuit 9, whose output is applied to the timing phase control circuit 2 and is also fed back to the multiplier 6. The other inputs to these multipliers come from the data output. The other input to the circuit 9 is from the output of the circuit 4, i.e. the received data with the intersymbol interference removed. The other inputs to the two multipliers come from the actual data output. Thus the output of this coefficient generation circuit depends on the characteristics of the equalised signal as presented to the threshold circuit 5 and on the actual data output.

The other coefficient generators are all similar except that they receive their inputs via successive one-unit delays 10, 1 1, 1 These other coefficients are summated in a summator 12, whose output forms the subtract input to the subtractor 4.

Thus one coefficient generator 6-7-8 controls the timing phase control, it having a further connection via which the output of the integrator 7 goes direct to the circuit 2, while the others control the subtraction of the interference due to the previous symbols.

The decision value due to a sample i, as leaving the threshold circuit 5 is D, so the decision value for the nth previous sample is Dl~n. The estimated value of the unit symbol response at t due to a symbol received at time is Cl~n. This estimate is referred to as the coefficient value, so the estimate of inter-symbol interference due to each previously received symbol at then is Dl~n Cj The sample value free of estimated post cursor (i.e. due to previous symbols) interference is thus applied to the threshold detector 5, which decodes the symbol value, 1 or -1 in the binary PCM case.The value which is then "outputted" from the subtraction circuit 4, and which is present at the detector decision circuit is thus:

where r1 is the data as received, and k is the number of coefficients summated by the summator 12. The decision value in the case of the binary system described here is the sign of k (dl=sgn (k;)).

The decision value of d1 is then multiplied by a coefficient representing the estimate of the channel response at the sample time. This product is then subtracted from the value at the input of the detector 5, and is termed the error value, which is thus formed on the basis of the following calculation:

The error estimate is reducible by the stochastic adjustment of the coefficient values.

Each coefficient is in effect incremented by a fraction of the error value, and the detected symbol value is used to form the product with that coefficient in deriving the error value. Thus we have: e1 Cl~n=Ci-nDl-n A The next sample is then taken, and the previously detected samples are shifted one cell through the memory formed by the series of unit delays 10, 11 etc. Thus the process repeats.

The timing control, represented by the box 2, is a switch which, under control of its inputs, sequentially steps the "sample" instruction in even steps from 0 to 360C relative to the master clock. At each step, the adaptive decision feedback equalisation coefficients are allowed a specific time to reach a state of dynamic equilibrium, and in the next n bits the tests defined below occur. If the result is satisfactory the sampling time is held constant, the test being repeated if needed. If the test fails, the sampling time is advanced to the next sampling phase. This process will rotate through all phases if no satisfactory phase is found, or the severity of the test is relaxed.

The coefficient derived from the correlator 6, 7, 8, called the cursor coefficient, represents the expected unit symbol magnitude, or peak eye magnitude at the decision point in the receiver.

The error estimate obtained, which is used to update the coefficients represents the amount of interference still remaining in the eye after the equalisation, and thus represents the degree of eye closure. Thus if the equaliser is interrogated at each decision when it has reached a dynamic equilibrium of convergence, the following criteria may be used to judge error performance.

The hypothesis on which the test is based is that the error probability of the magnitude of the error estimate exceeding the cursor coefficient is proportional to the receiver error probability. Thus for example if the distribution of the error estimate is assumed to be Gaussian, the distribution could be characterised by its mean and variance. The means is inherently zero due to the adaption process. The variance may be calculated by summation of the square of the error estimate over n symbols. By reference to the Gaussian probability distribution, it may be seen that a limiting ratio can be defined which must not be exceeded for a particular bit error rate. A description of two methods of implementation follows.

The ratio of the mean value of the cursor coefficient is compared with the mean value taken over n symbols of a weighted function of the error estimate, the assumption made is that from a sample of n digit periods of parameters describing the error estimate distribution may be obtained. The value of the ratio thus defines the equaliser performance and a limiting lower bound may be set for this value, the instruction to step the timing phase is generated when this limit is exceeded.

A second implementation has been based on the frequency at which a threshold lower than the cursor coefficient is exceeded in magnitude by the error estimate. Figure 2 represents in schematic form the system. The cycle of operation begins following a change of phase instruction or switch on. A specific period of time is necessary following a timing phase change for the equaliser to adapt to the channel characteristic and attain a dynamic equilibrium, thus the counter is zeroed and disabled for M symbol periods at the start of the cycle. The magnitude of the error estimate and the magnitude of the cursor coefficient by the comparator circuit 2i. For each occurrence of the error estimate magnitude exceeding the value of the scaled cursor coefficient magnitude a count is registered by the counter circuit 23. When the count exceeds the threshold set by circuit 25 the digital comparator circuit 24 generates a pulse which shifts the timing phase and restarts the cycle of operation, the output pulse indicates the error rate is not satisfactory as defined by the expected statistics of the error estimate. If after n symbols the counter circuit 23 has not exceeded the threshold as defined by circuit 25 the counter is reset to zero and immediately begins another count for the next n symbol periods and this is repeated indefinitely.

Claims

1. An adaptive equaliser for equalising received digital data, in which the received data is applied via a sampling circuit to a subtraction circuit whose circuit output is applied to a threshold detector the output of which, digital 1 or 0, is the output of the equaliser, in which a number of coefficient generation circuits are provided which generate coefficients dependent on the value of a corresponding number of preceding digital bits, in which a summation circuit summates said coefficients and applies the result of said summation to the other input of the subtraction circuit so that the latter produces an output representing the value of the current sample less interference due to preceding sampler, in which a further coefficient generation circuit generates, under the control of the current sample and its output a coefficient whose value is used to adjust the sampling instant within the received symbol period, and in which the output of the subtraction circuit is applied to the threshold detector.

2. An equaliser as claimed in claim 1, and in which each said coefficient generator is a sequential arrangement of a multiplier, an integrator and another multiplier.

3. An equaliser as claimed in claim 1 or 2, and in which the coefficients generation for the coefficients dependent on preceding sampled bits are controlled via a sequential one bit delay which thus forms a memory of said preceding sampled values.

4. An adaptive equaliser, substantially as described with reference to the accompanying drawings.