GB2080780A - Heat treatment of silicon slices - Google Patents
Heat treatment of silicon slices Download PDFInfo
- Publication number
- GB2080780A GB2080780A GB8121544A GB8121544A GB2080780A GB 2080780 A GB2080780 A GB 2080780A GB 8121544 A GB8121544 A GB 8121544A GB 8121544 A GB8121544 A GB 8121544A GB 2080780 A GB2080780 A GB 2080780A
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- United Kingdom
- Prior art keywords
- slice
- process according
- silicon
- range
- hours
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 34
- 239000010703 silicon Substances 0.000 title claims abstract description 34
- 238000010438 heat treatment Methods 0.000 title description 17
- 238000000034 method Methods 0.000 claims abstract description 32
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000001301 oxygen Substances 0.000 claims abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 19
- 230000007547 defect Effects 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000001816 cooling Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000011282 treatment Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000002244 precipitate Substances 0.000 description 11
- 235000012431 wafers Nutrition 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000008367 deionised water Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000007605 air drying Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910000953 kanthal Inorganic materials 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
- C30B31/06—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor by contacting with diffusion material in the gaseous state
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
A process of heat treating silicon slices to remove microdefects from the surface comprises the following steps:- (a) heat above 1,100 DEG C from a time sufficient to allow oxygen to diffuse from the surface region, (b) heat between 550 DEG C to 950 DEG C to allow defects to nucleate in the bulk of the slice, (c) cool below 300 DEG C. The time for step (a) and for step (b) is in the range 2 to 24 hours. The treated slice has a surface region substantially defect free in which integrated circuits may be formed.
Description
SPECIFICATION
Manufacture of electronic devices on silicon
This invention relates to the manufacture of electronic devices on silicon, particularly the preparation of slices of silicon prior to device manufacture.
Electronic devices, such as diodes, transistors, integrated circuits, charge coupled devices, etc., are formed on the surface of a semiconductor material by processes involving the growth of differently doped, p or n-type layers on a flat surface i.e. planar technology. Epitaxial processes involve the growth of an active layer on a suitable substrate which acts as a support. Other processes involve preparing a device in the top few microns of a bulk semiconductor material i.e. the active region. Both techniques require high purity, accurately doped and defect free bulk material. The present invention concerns devices in which the active region is formed in the top of a bulk silicon slice (MOS circuits) or in an epitaxial layer.
The majority of present day integrated circuits are fabricated on polished silicon wafers which are prepared from single crystal silicon growth by the
Czochralski pulling technique. This technique can produce both n-type and p-type silicon for any desired electrical resistivity below 50Q cm. For crystals with a target resistivity of greater than 18 cm the electrical resistivity of the as-grown crystal frequently differs significantly from the target resistivity. The discrepancy is usually due to the formation of so-called oxygen donor (or thermal donor) complexes.The complexes are formed by the reaction of oxygen impurities with the silicon at tempera- tures within the range 500-300 C. The complexes are unstable at temperatures above 60000. All current
Czochralski silicon contains oxygen as an impurity (the oxygen impurity arises from reaction of the molten silicon with the silica crucible during the growth of the crystal), and as the crystal cools through the temperature range 500-300 C all
Czochralski grown silicon contains donor complexes.
These complexes alter the resistivity of the silicon and because the number of complexes formed depends on the heat treatment which the silicon has received the resistivity of the silicon is found to vary with heat treatment.
In order to ensure that the resistivity of the silicon in the absence of the oxygen donor complex meets the customers' requirement, it is necessary to destroy oxygen donors. This is achieved by heating the silicon to some temperature greater than 600"C, and then cooling the crystal rapidly through the tempera- ture range 500-300 C. Details of the procedure and treatment used varies between manufacturers but generally times of between 1 to 5 hours and temperatures between 650 C and 800 C are used.
For crystals with diameters of about 5 cm and less the heat treatment is generally carried out before the crystal is cut into slices.
For crystals greater than about 5 cm the process is generally carried out after the crystal has been processed into wafers. In some cases the heat treatment is made both to the crystal and to the wafer.
In cases where the target resistivity is less than about 1 Q cm the effects of the oxygen donors are insignificant and such heat treatments are not necessary.
Unfortunately this necessary heat treatment results in micro-defects that are scattered throughout the whole material. Such defects, when occurring in the active region near the surface, result in inferior device performance or even complete failure in large integrated circuits.
The present invention improves device performance by removing microdefects from the active region in a silicon slice.
As used hereinafter a slice of silicon or silicon slice means a thin piece or wafer of silicon cut from a single crystal of silicon grown by the Czochralski method.
According to this invention a process for treating a slice of silicon for subsequent device manufacture comprises the steps of:
(a) heat treating the slice at a temperature above 110000 in a furnace for a time sufficient for oxygen to diffuse from the surface regions; followed by
(b) heat treating the slice in a temperature between 55000 to 95000 for a time sufficient to nucleate defects; and
(c) cooling the slice to below 300 C.
Subsequent processing steps may include polishing and cleaning prior to growth of device structure.
Alternatively an oxide layer may be thermally grown before or after step (c).
The heat treatment may be carried out in an inert atmosphere e.g. argon, an oxidising atmosphere, or in a vacuum.
Step (a) may be at a temperature in the range 1 1500coo 1350'C for 2-24 or more hours. Step (b) may be for a time of 2-24 hours or so depending on original oxygen content at a temperature between 65000 to 85000.
Thermal donors are stabilised in the above process.
Conventionally crystals grown by the Czochralski method are ground to required diameter, sliced etched and polished, and heat treated at 650#8500C followed by a rapid cooling. This heat treatment may take place before the slicing. The first device manufacturing step is usually growth of an oxide layer by heating in a oxidising atmosphere at e.g. 1 1500for 3 hours. This oxide layer is used as a mask for later stages of manufacture.
Silicon crystals when grown by the Czochralski method contain micro defects distributed throughout the crystal. The microdefect is a precipitate, believed to be an oxide of silicon. During resistivity heat treatment the precipitate may either grow or shrink dependent on whether or not the matrix close to the precipitate is supersaturated with oxygen.
Low temperatures, high oxygen content and large precipitates will all favour precipitate growth. If the matrix is not supersaturated with respect to the precipitate then the precipitate will shrink. Also, during the oxide layer growth some precipitates may grow whilst others shrink near the surface of the slice.
The preparation of silicon slices according to this invention will now be described by way of example only.
The following steps are taken:
1. Grow crystal of silicon by the Czochralski method. Grind to required diameter e.g. 5cm or 7.6cm; slice into thin wafers e.g. 375iim thick, using a diamond saw; round the slice edges by grinding; chemically clean and rinse with de-ionised water; etch with e.g. HF and HNO3 mixture to remove work damage; polish with a suspension of silica and
NaOH on a lap; and clean e.g. with HF and H2SO/
H202 then rinse with deionised water.
2. Heat treat in a standard oxidisation/diffusion furnace. This has a double walled silica furnace tube heated by a kanthal filament, the atmosphere is high purity argon. The heat treatment temperature is above 11 000C e.g. 1150-1 2500C and lasts for e.g.
4-16+ hours typically 16 hours. During this time oxygen diffuses out from the slice surfaces leaving an oxygen gradient which is supersaturated in the middle of the slice thickness varying to a level below that at which the defects will grow at the slice surface. To reduce the time of heat treatment the temperature may be above 12500C e.g. 13500C in a silica carbide furnace.
3. Heat treat in the above furnace at a tempera ture between 650-850"C for e.g. 14-16 hours. This stabilises the resistivity but most importantly it also allows the microdefects to nucleate and grow. Since the oxygen saturation varies across the slice thickness those microdefects in the centre of the slice grow whilst those near the surface shrink. This results in a layer near the surface that is substantially defect free and it is this region that forms the active region or provides a defect free surface for subsequent epitaxiai growth in subsequent device manufacture. The growth of micro defects provide a gettering action i.e. a process by which the micro defects remove harmful impurities away from active regions of a slice.
4. Clean by immersion in H2SOdjH202 and rinse in deionised water followed by air drying.
The slice is now suitable for device manufacture.
For example a silicon oxide layer may be thermally grown on the slice surface then, using known photo lithographic techniques, areas of differently doped silicon may be grown on the surface through holes opened in the oxide layer. Further layers of silicon oxide and doped silicon and or metal may be grown or deposited to form e.g. diodes, transistors, etc., or various integrated circuits such as charge coupled devices, memories, microprocessors, etc.
In a modification to the above the polishing step may be carried out after the two heat treatments.
An example of the process according to this invention will now be described with reference to the accompanying photographs of which:- Figure 1 shows a cross section of a silicon slice not treated according to the present invention;
Figure2 shows a cross section of a silicon slice heat treated according to the present invention.
To provide the slices shown as grown unannealed polished wafers were prepared from the seed and tail ends of a dislocation free 5.7cm diameter < 100 > p-type Czochralski grown crystal. The slices were cleaned and given the following heat treatment.
Sample A, Figure 1. Annealed at 7500C for 16 hours then 1 150"C for 16 hours followed by oxidation at 11 50"C for 251/2 minutes.
Sample B, Figure 2. Heat at 1 150"for for fli6 hours then 7500C for 16 hours followed by oxidation for 251/2 minutes. The slices were also metallised with aluminium for later capacitance measurements but the temperature and time, 450"Cfor for 15 minutes, is insufficient to affect the microstructure.
Both slices (seed end slices) samples A, B, were cleaned and given a 5 minute Wright etch before being photographed atX430 magnification.
In sample A Figure 1 etch pits from dislocation loops associated with oxygen precipitates are visible in the slice cross section extending to the surface; the defect distribution is also inhomogeneous.
In sample B Figure 2 etch pits are also present but have a more uniform distribution and do not extend to the surface; there is a denuded zone extending about 30 cm from the surface.
In both samples A, B the dislocations are produced by the growth of silicon oxide precipitates during the heat treatments. The cross sectional microstructure is different in the two samples, however,. because in sample B the high initial temperature (1 150"C) treatment denudes the surface of oxygen below the concentration at which precipitates and subsequently dislocations form, whilst in sample A in which the sequence of steps (a) and (b) have been reversed the defects extend to the surface of the slice. This is because the defects are formed before the surface is depleted of oxygen.
Claims (14)
1. A process for treating a slice of silicon for subsequent device manufacture comprises the steps of:
(a) heat treating the slice at a temperature above 1100 C in a furnace for a time sufficient for oxygen to diffuse from the surface regions; followed by
(b) heat treating the slice in a temperature between 5500C to 9500C for a time sufficient to nucleate defects; and
(c) cooling the slice to below 300 C.
2. The process according to claim 1 wherein the step (a) temperature lies in the range 11 50"C to 13500C.
3. The process according to claim 1 or 2 wherein the time in step (a) is in the range 2 to 24 hours.
4. The process according to any one of claims 1 to 3 wherein the step (b) temperature lies in the range 650"C to 850 C.
5. The process according to any one of claims 1 to 4 wherein the time in step (b) is in the range 2 to 24 hours.
6. The process according to claim 3 wherein the time is in the range 4 to 16 hours.
7. The process according to claim 5 wherein the time is in the range 4to 16 hours.
8. The process according to any. one of c, lai=ms 1 to 7 wherein the treatmentis ##). < +
'-..#..#..
atmosphere.
9. The process according to any one of claims 1 to 7 wherein the treatment is carried out in a vacuum.
10. The process according to any one of claims 1 to 9 wherein the slice is polished and cleaned prior to step (a).
11. The process according to claim 10 wherein an oxide layer is thermally grown before or after step (c).
12. The process according to any one of claims 1 to 11 further comprising the steps of providing differently doped areas of silicon on or in the slice to form a semiconductor device.
13. A semiconductor device prepared using the process of claim 12.
14. The process of treating a slice of silicon according to claim 1 substantially as hereinbefore described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8121544A GB2080780B (en) | 1980-07-18 | 1981-07-13 | Heat treatment of silicon slices |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8023539 | 1980-07-18 | ||
| GB8121544A GB2080780B (en) | 1980-07-18 | 1981-07-13 | Heat treatment of silicon slices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2080780A true GB2080780A (en) | 1982-02-10 |
| GB2080780B GB2080780B (en) | 1983-06-29 |
Family
ID=26276264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8121544A Expired GB2080780B (en) | 1980-07-18 | 1981-07-13 | Heat treatment of silicon slices |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2080780B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0090320A1 (en) * | 1982-03-26 | 1983-10-05 | International Business Machines Corporation | A method for tailoring oxygen precipitate particle density and distribution in silicon |
| US4459159A (en) * | 1982-09-29 | 1984-07-10 | Mara William C O | Method for making semi-insulating substrate by post-process heating of oxygenated and doped silicon |
| FR2543981A1 (en) * | 1983-04-08 | 1984-10-12 | Hitachi Ltd | PROCESS FOR PRODUCING SEMICONDUCTOR MATERIALS AND PROCESSING FURNACE FOR CARRYING OUT SAID METHOD |
| US4505759A (en) * | 1983-12-19 | 1985-03-19 | Mara William C O | Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals |
| US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
| US4622082A (en) * | 1984-06-25 | 1986-11-11 | Monsanto Company | Conditioned semiconductor substrates |
| US4666532A (en) * | 1984-05-04 | 1987-05-19 | Monsanto Company | Denuding silicon substrates with oxygen and halogen |
| EP0390672A2 (en) * | 1989-03-31 | 1990-10-03 | Shin-Etsu Handotai Company Limited | Method for heat process of silicon |
| EP0496382A2 (en) * | 1991-01-22 | 1992-07-29 | Nec Corporation | Intrinsic gettering for a semiconducteur epitaxial wafer |
| EP0503816A1 (en) * | 1991-03-15 | 1992-09-16 | Shin-Etsu Handotai Company Limited | Heat treatment of Si single crystal |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP0732431A1 (en) * | 1995-03-14 | 1996-09-18 | MEMC Electronic Materials, Inc. | Precision controlled precipitation of oxygen in silicon |
| US5629216A (en) * | 1994-06-30 | 1997-05-13 | Seh America, Inc. | Method for producing semiconductor wafers with low light scattering anomalies |
| US5885905A (en) * | 1992-07-17 | 1999-03-23 | Kabushiki Kaisha Toshiba | Semiconductor substrate and method of processing the same |
| EP1284311A2 (en) * | 2001-08-09 | 2003-02-19 | Wacker Siltronic Gesellschaft für Halbleitermaterialien Aktiengesellschaft | Silicon semiconductor substrate and process for producing the same |
-
1981
- 1981-07-13 GB GB8121544A patent/GB2080780B/en not_active Expired
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0090320A1 (en) * | 1982-03-26 | 1983-10-05 | International Business Machines Corporation | A method for tailoring oxygen precipitate particle density and distribution in silicon |
| US4459159A (en) * | 1982-09-29 | 1984-07-10 | Mara William C O | Method for making semi-insulating substrate by post-process heating of oxygenated and doped silicon |
| FR2543981A1 (en) * | 1983-04-08 | 1984-10-12 | Hitachi Ltd | PROCESS FOR PRODUCING SEMICONDUCTOR MATERIALS AND PROCESSING FURNACE FOR CARRYING OUT SAID METHOD |
| US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
| US4505759A (en) * | 1983-12-19 | 1985-03-19 | Mara William C O | Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals |
| WO1985002940A1 (en) * | 1983-12-19 | 1985-07-04 | Mara William C O | Method for making a conductive silicon substrate and a semiconductor device formed therein |
| US4666532A (en) * | 1984-05-04 | 1987-05-19 | Monsanto Company | Denuding silicon substrates with oxygen and halogen |
| US4622082A (en) * | 1984-06-25 | 1986-11-11 | Monsanto Company | Conditioned semiconductor substrates |
| EP0390672A2 (en) * | 1989-03-31 | 1990-10-03 | Shin-Etsu Handotai Company Limited | Method for heat process of silicon |
| EP0390672A3 (en) * | 1989-03-31 | 1991-08-28 | Shin-Etsu Handotai Company Limited | Method for heat process of silicon |
| US5110404A (en) * | 1989-03-31 | 1992-05-05 | Shin-Etsu Handotai Co., Ltd. | Method for heat processing of silicon |
| EP0496382A2 (en) * | 1991-01-22 | 1992-07-29 | Nec Corporation | Intrinsic gettering for a semiconducteur epitaxial wafer |
| EP0496382A3 (en) * | 1991-01-22 | 1993-08-04 | Nec Corporation | Intrinsic gettering for a semiconducteur epitaxial wafer |
| EP0503816A1 (en) * | 1991-03-15 | 1992-09-16 | Shin-Etsu Handotai Company Limited | Heat treatment of Si single crystal |
| US5834322A (en) * | 1991-03-15 | 1998-11-10 | Shin-Etsu Handotai Co., Ltd. | Heat treatment of Si single crystal |
| US5885905A (en) * | 1992-07-17 | 1999-03-23 | Kabushiki Kaisha Toshiba | Semiconductor substrate and method of processing the same |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP0635879A3 (en) * | 1993-07-22 | 1996-10-23 | Toshiba Kk | Semiconductor silicon wafer and process for its production. |
| US5738942A (en) * | 1993-07-22 | 1998-04-14 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| US5629216A (en) * | 1994-06-30 | 1997-05-13 | Seh America, Inc. | Method for producing semiconductor wafers with low light scattering anomalies |
| EP0732431A1 (en) * | 1995-03-14 | 1996-09-18 | MEMC Electronic Materials, Inc. | Precision controlled precipitation of oxygen in silicon |
| US5593494A (en) * | 1995-03-14 | 1997-01-14 | Memc Electronic Materials, Inc. | Precision controlled precipitation of oxygen in silicon |
| EP1284311A2 (en) * | 2001-08-09 | 2003-02-19 | Wacker Siltronic Gesellschaft für Halbleitermaterialien Aktiengesellschaft | Silicon semiconductor substrate and process for producing the same |
| EP1284311A3 (en) * | 2001-08-09 | 2003-03-05 | Wacker Siltronic Gesellschaft für Halbleitermaterialien Aktiengesellschaft | Silicon semiconductor substrate and process for producing the same |
| US6805742B2 (en) | 2001-08-09 | 2004-10-19 | Siltronic Ag | Silicon semiconductor substrate and process for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2080780B (en) | 1983-06-29 |
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