GB2080582A - Procedure and apparatus for conveying external input and output data to a processor system - Google Patents

Abstract

For conveying the input and output data of a process or of other computer-controlled apparatus or equipment to a processor system comprising one or several central units (4) with memories (5), the input and output data (I/O) are separated from the central units by means of I/O memories (3). The data transfer between the input and output data matching unit (2) and the I/O memories (3) is performed by an I/O copier (1). The copier is a processor which copies data from an input multiplexer to the input memory section of each central unit simultaneously, and copies output data from each central unit to the input/output memories of all the units. <IMAGE>

Description

SPECIFICATION Procedure and apparatus for conveying external input and output data to a processor system The present invention concerns a procedure for conveying to a processor system the input and output data of a process or of other computorcontrolled pieces of apparatus or installations, said system comprising one or several central units with memories.

In numerous control systems, implemented by the aid of computers, of processes or of complex equipment, e.g. of cranes or of entire installations, it is sensible to distribute various tasks among the different central units. It is similarly worthwhile to subdivide also various controls of parts of apparatus or of entire apparatus units. Hereby is achieved easy programmability and a clear system, which is easy to service and to modify. In order that in this test no conceptual obscurities might arise, it is proper to specify precisely the terms "computer", "central unit" and "processor" from the viewpoint of the present invention. A computer is understood to be an entity composed of one or several central units with ancillary equipment and the central unit, again, consists of one or several processors with ancillary equipment.In the control systems mentioned, frequently two or more central units need the same input and output data from a processor, or regarding the state of the apparatus at a given time. For instance, the action datum of one and the same limit switch may be needed by one or several central units so that the control might be properly managed.

In prior art, this problem in control systems has been solved, either by connecting all requisite input and output data directly to all central units needing them or by connecting the central units together by means of some kind of data transfer bus, or even by using a separate input/output processor (to be referred to briefly as I/O processor in the following), by mediation of which all central units receive all the data which they need. All these arrangements have their own drawbacks, however: when the input and output data are directly connected to all central units, it becomes necessary to construct for all of them similar input and output circuits. This increases the manufacturing costs and renders the circuitry complex.If each input and output datum is connected to only one central unit and a data transfer bus is used, these costs may be reduced, but now arises the problem of the interfacing between central units, the costs thereby incurred, and often also the slow operation caused by the bus. On the other hand when an I/O processor is used, there appear as extra costs those of the I/O processor itself, and the problem is then the interfacing of the central units and the I/O processor, in the first place as regards the speed of operation which it permits when there are several central units. For taking care of such interfacing, DMA (Direct Memory Access) technique or the traditional I/O technique has been used.

The purpose with the procedure and apparatus of the invention is to eliminate all the above-mentioned drawbacks and to provide a reliable control system, and one which is inexpensive in its manufacturing costs, for processes and for complex apparatus. The procedure of the invention is characterised in that the input and output data are separated from the central units by I/O memories and that the data transfer between the input and output data matching unit and the I/O memories is carried out by an I/O copier. The advantage is then that the l/O bus does not burden the central units thereto connected, and that the number of central units that can be connected to one bus is only limited by the elctrical loading capacity of the bus. It is a further advantage that the input and output circuits need not be multiplied.All these favourable features make possible the outcome that the manufacturing costs of an installation carrying out the procedure will be low.

An advantageous embodiment of the invention is characterized in that the I/O copier copies the data from an input multiplexer to the input memory section of each central unit simultaneously and that it copies the output block of each central unit both to the output memories and to the equivalent block of the other central units simultaneously. The advantage is then that the synchronisation of the data processing processes performed by the central units is facilitated because the I/O copier simultaneously updates the data in all I/O memories.

Another advantageous embodiment of the invention is characterized in that the I/O copier performs data transmission without interruption while the system is in operation. This affords the advantage, among other things, that inversion of state of the output circuit due to a disturbance will be automatic- ally corrected.

A third favourable embodiment of the invention is characterized in that the updating of the input data to the I/O memories and the updating of output data from the I/O memories is accomplished completely without burdening the central units. This affords above all the advantage that one central unit may have a plurality of I/O buses, and these buses impose no load on it.

Still another favourable embodiment of the invention is characterized in that the data transfer between the I/O memories and the matching unit is accomplished in series mode, 1 ...n bits in parallel.

Still one favourable embodiment of the invention is characterized in that the addressing of data in the copying event is executed for the I/O memories and the matching unit with the aid of separate address counters which are synchronized by the I/O copier.

The advantage common to these two embodiments is that the I/O bus can be kept narrow because no address data need be transmitted therein. Moreover, as a result of the narrow bus and of its permissible slowness, the bus and the central units thereto connected may be galvanically isolated with comparative ease, thus reducing the manufacturing costs.

Still one favourable embodiment of the invention is characterized in that the timing of the interfacings is detached from the timing of the central units. The advantage is then gained that the I/O bus has a good interference tolerance because fairly slow signals could be permitted for use therein.

The invention also concerns apparatus for car rying out the procedure mentioned above. The apparatus comprises one or several central units with memories, and an input and output data matching unit. The apparatus of the invention is characterized in that to the I/O bus after the matching unit has been connected for each central unit a simple I/O memory, which is connected by a local bus further to the central unit, and that the copier transmitting both input and output data has been connected to the same bus with the matching unit and the I/O memories. The advantage is then gained that the I/O bus imposes no load on the central units thereto connected. It is a further advantage that the central units can read all inputs and write to all outputs by normal memory reading and writing operations.Furthermore, the central units may also read the states of all outputs from the I/O memories.

Afurther advantage is the low price of the apparatus.

For instance, the simple I/O copier which is employed is substantially more advantageous than the commonly used, more complex I/O processors.

In the following, the procedure of the invention and the operation of the apparatus of the invention shall be described in greater detail with the aid of an example, with reference being made to the attached drawings, wherein: Figure 1 presents the circuit of the invention, as a block diagram.

Figure 2 illustrates the copying event accomplished by the I/O copier.

Figure 3 shows the I/O memory with its ancillary circuits, as a block diagram.

Figure 4 shows the I/O copier with its ancillary circuits, and Figure 5shows the input and output data matching unit and its circuit, as a block diagram.

In the circuit of the invention is used an exceedingly simple I/O processor, which is here called the 110 copier 1, and which conveys the data from the inputs and outputs between the 110 memories 3 and the input and output data matching unit 2. The data transfer takes place along a common I/O bus 6 between all central units 4 and the input and output data matching unit 2. The interfacing from the I/O bus to the central units 4 has been made by mediation of each central unit's 4 own so-called I/O memory 3, this again being connected to its central unit 4 by a local bus 7. The I/O bus is driven at a frequency so slow, and synchronized with the central units 4, that the use of the central unit's 4 1/O memory 3 has no effect on the operation of the l/O bus 6.

The I/O copier 1 continuously copies inputs to the I/O memories and outputs from the I/O memories 3.

In other words, the I/O copier continuously runs through the same loop. The copying event itself is illustrated by Figure 2, and the I/O copier 1, not visible in the Figure, copies all input data one word at a time simultaneously from the input multiplexer 11 to the I/O memories 3 of all central units 4, more precisely told to their input memory section 16. One word comprises 1 ...n bits, with n a positive integer.

Thus, therefore, all central units 4 receive the data of all inputs simultaneously in their I/O memories. The output memory sections 17 of the I/O memories and the output memory sections 12 of the input and output data matching unit 2 have been divided, in Figure 2, into blocks according to output group, and each such block may comprise 1 ...n words. The number of blocks is not dependent on the number of central units or of input data, but it is not sensible in practice to make the number of blocks greater than that of central units. The blocks, or output groups, have been differently hatched in Figure 2 for greater clarity.

The blocks indicated by the hatching A represent output groups to which e.g. the central unit 4.1 is A permitted to write; while those indicated by the # hatching B may be written to by the central unit 4.2; and the central unit 4.m may write to those indicate3 with the hatching C. From all blocks of the own I/O memory 3, all central units 4.1 ...4.m are allowed to read. If each word that is going out, comprising 1...n bits, or each output group, comprising 1...n words, is being updated by several central units 4, the setting of the output's state depends on the electrical logics used. Thus each central unit has its own, preselected output group.The I/O copier copies the outputs, one word at a time, to the output memories 12 of each output group and to the output section (17) of the I/O memories in all other central units, to the equivalent location simultaneously. In other words, the outputs of one central unit are as inputs to the others. All other central units thus receive simultaneously information concerning the states of the outputs.

The central unit 4 may read and write to the I/O memory 3, to its own permitted areas, at any time.

Thus the central unit 4 is not compelled to wait for data from the bus 6, nor for the becoming free of the respective bus, as is the case in all other solutions known in the art. In order that the I/O memory 3 might not be able to hook into the bus of two different "pieces of apparatus" - in the present instance of the central unit 4 and the I/O bus 6 - when it is in use, the operation of the bus 6 and the central unit 4 has to be so synchronized that their addressing changes cannot occur simultaneously. Since the bus 6 is common to all central units 4, these all have to be synchronized with the bus 6. The synchronizing may be carried out e.g. in that the central units 4 and the I/O copier 1 are driven with ? the same clock signal 8 and they use different edges of the clock pulse for changing of addressing.Again; in order that the I/O circuits, or the input and output, data circuits (I,O), and the addressing of the I/O memories 3 on the side towards the bus 6 might be kept in step with each other, they have to be synchronized. This could be managed in that the I/O copier 1 would create addresses for them all simultaneously, but in order that the bus 6 could be kept narrow, each 110 memory 3 and I/O circuit generates its address itself, and the I/O copier 1 keeps the address counters 18,13 in step by generating for them all a common clock signal 8 and furthermore for start-up situations and for making sure of synchronizing, it generates for all a common synchronizing signal 9. In order that the manipulation of the I/O memory 3 of the central unit 4 might not be visible on the bus 6, or vice versa, the timing of their read or write events has been managed so that one or the other - as a rule the bus - is slower than the other in such degree that the other may interrupt its read or write operation and perform its own read or write operation in a manner such that it is not "visible" at all to that which is slower. For instance, if the memory period of the central unit is 1/10 of the memory period of the bus, this interruption of 1/10 in the period of the bus will have no effect on the operation of the bus.

Figure 3 displays the construction of the I/O memory 3 and its connection to the rest of the system, in a block diagram. What is concerned here is a RAM type memory 21 with double ports both on the address 19,27 and the data lines 20,28. Through one set of ports 29, the central unit 1 reads the memory or writes thereto, and through the other set of ports 30 the memory communicates with the I/O bus 6 and the address counter 18. Only when the central unit wishes to use the memory are the ports towards the bus 7 active. The address counter 18 counts the address 21 in the step of the clock signal 8 coming to the memory 21 from the bus 6. The address has been connected to the memory 21 through the ports 30, which are active at all times other than those when the central unit 4 desires to use the memory 21.The counter 18 is synchronized with the respective address counters of the other I/O memories 3 by the synchronizing signal 9. The unit 22 may be called the I/O write/read selection and timing unit. This is a logics unit by the aid of which the input and output areas are selected from the memory 21. The unit 22 generates the read or write signals and performs the timing of these and of the addresses. The outgoing data holding unit 23 takes care that the data remains unchanged on the bus 6 in case the central unit 4 desires to use the RAM memory while writing to the bus 6 is in progress.

The bus buffers 24 are circuits which match the RAM memory 21 to the I/O bus 6 to be electrically matched.

The central units 4 to be connected to the bus 6 and the copying event must be synchronisable so that the changes of state of the address counters 18 of the I/O memories 3 of the central units 4 will not occur at the same time. Therefore the central units have to be mutually synchronized so that there are such time intervals during which no changes take place in that bus 7 of the central unit 4 on which it addresses the I/O memory 3 and in which time intervals the changes of the address counters 18 are effected, that is the moments of change of the signal 8. This is taken care of by the I/O copier's synchronous clock generator 25, which may also be replaced with the clock pulse 31 of any one central unit 4 and by which all other central units and the 110 copier 1 are synchronized.The I/O copier 1 also comprises the divider 26, which is a simple counter dividing from the synchronous clock pulse 10 a clock pulse 8 of suitable frequency to the I/O bus 6, and generates at predetermined intervals the I/O synchronizing signal 9 by which the address counters 18 of all RAM memories 21 are synchronized. For instance, when the RAM memory 21 has been run through once, the I/O synchronizing signal 9 may be a mere zeroing pulse for the address counters 18. The maximum frequency of the clock pulse 8 is determined by the clock frequency of the central units 4 and by the length of their memory periods.

Figure 5 illustrates the construction of the input and output data matching unit 2 and its connection with the rest of the system, in a block diagram.

Herein, the I/O address counter 13 counts addresses to the input multiplexer 11 and to the output memory section 12 in step with the clock pulse 8 coming from the bus 6. With the aid of the I/O synchronizing signal 9, the address counter 13 is synchronized with the address counters 18 of the I/O memories 3. The unit 14 is the read/write selection and timing unit. It is a logics unit which selects the read or write operation and generates the requisite read and write pulses. The input multiplexer 11 is controlled both by the address counter 13 and by the read pulses. The output memory section 12, again, contains the addressable memories which are controlled by the address counters 13 and the write pulses, and finally the bus buffers 15 are circuits which electrically match the inputs and outputs to the I/O bus 6.

It is obvious to a person skilled in the art that the invention is not exclusively confined to the example related above, and that rather its embodiments may vary within the scope of the claims presented hereinafter.

Claims (10)

1. Procedure for conveying the input and output data of a process or of other computer-controlled apparatus or equipment to a processor system comprising one or several central units (4) with memories (5), characterized in that the input and output data (I/O) are separated from the central units by means of I/O memories (3) and that the data transfer between the input and output data matching unit (2) and the I/O memories (3) is performed by an I/O copier (1).

2. Procedure according to claim 1, characterized in that the 110 copier (1) copies the input data from an input multiplexer (11 ) to the input memory section (16) of each central unit (4) simultaneously and that it copies the output block (17) of each central unit (4) both to the output memories (12) and to the equivalent block of the other central units (4) simultaneously.

3. Procedure according to claim 1 or 2, characterized in that the I/O copier (1 ) carries out data transmitting without interruption while the system is in operation.

4. Procedure according to claims 1-3, characterized in that the updating of input data to the I/O memories (3) and the updating of the output data from the 110 memories (3) is carried out completely without burdening the central units (4).

5. Procedure according to claim 1-4, characterized in that the data transfer between the matching unit (2) of the I/O memories (3) is performed in series mode, 1...n bits in parallel.

6. Procedure according to claims 1-5, characterized in that the addressing of the data in the copying event is carried out for the I/O memories (3) and the matching unit (2) with separate address counters (13,18), which are synchronized by the I/O copier (1).

7 Procedure according to claims 1-6, characterized in that the timing of the interfaces is detached from the timing of the central units (4).

8. Apparatus for carrying out a procedure according to claim 1, comprising one or several central units (4) with memories (5) and an input and output data matching unit (2), characterized in that to the bus (6) after the matching unit (2) has been connected for each central unit (4) a simple I/O memory (3), which is by a local bus (7) connected further to the central unit (4), and that the I/O copier (1 ) transmitting input and output data is connected to the same bus (6) with the matching unit (2) and the I/O memories (3).

9. Procedure for conveying the input and output data of a process or of other computer-controlled apparatus or equipment to a processor system substantially as described herein.

10. Apparatus for carrying out the procedure as claimed in claim 1 substantially as described herein with reference to the accompanying drawings.