GB2077993A - Low sheet resistivity composite conductor gate MOS device - Google Patents
Low sheet resistivity composite conductor gate MOS device Download PDFInfo
- Publication number
- GB2077993A GB2077993A GB8109247A GB8109247A GB2077993A GB 2077993 A GB2077993 A GB 2077993A GB 8109247 A GB8109247 A GB 8109247A GB 8109247 A GB8109247 A GB 8109247A GB 2077993 A GB2077993 A GB 2077993A
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- United Kingdom
- Prior art keywords
- layer
- polysilicon
- conductive layer
- metal
- substrate
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- 239000002131 composite material Substances 0.000 title claims description 10
- 239000004020 conductor Substances 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 12
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 7
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 6
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 6
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims 2
- 230000008021 deposition Effects 0.000 abstract description 4
- 229910001092 metal group alloy Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 6
- 229910021352 titanium disilicide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- MANYRMJQFFSZKJ-UHFFFAOYSA-N bis($l^{2}-silanylidene)tantalum Chemical compound [Si]=[Ta]=[Si] MANYRMJQFFSZKJ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021343 molybdenum disilicide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical group 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The gate electrode of a MOS device comprises a layer 26 of a highly conductive material interposed between two polysilicon layers 14,18. This provides a gate electrode of reduced sheet resistivity. The highly conductive material may be a metal silicide formed by depositing a layer of a metal alloy or metal (eg Ti, Ta, W, Pt or Mo) on the first polysilicon layer 14, covering with the second polysilicon layer 18 and heating to react the metal with the polysilicon. Alternatively a metal silicide layer may be formed by direct deposition. <IMAGE>
Description
SPECIFICATION
Low sheet resistivity composite conductor gate
MOS device
The present invention relates generally to MOS devices, and more particularly to silicon-gate MOS devices.
Silicon gate MOS devices in which a doped polycrystalline silicon, or polysilicon, layer serves as the gate electrode are widely used in a wide variety of MOS integrated circuits, such as read-only memories and random-access memories. The speed of silicon-gate MOS devices has heretofore been limited by, among other things, the relatively high polysilicon sheet resistivity, which is typically in the order of 15 to 40 ohms per square. Since the speed of operation of an MOS circuit is dependent on RC time constants within the circuit, the relatively high level of sheet resistivity of the conventional silicongate devices limits the speed of operation of integrated circuits which contain these devices.
Although the desirability of reducing the sheet resistivity of silicon-gate MOS devices to increase the operating speed of these devices has long been recognized in the semiconductor industry, a success- ful and practical means of reducing the sheet resistivity, thereby reducing the RC time constant and increasing operating speed, has thus far not been achieved.
In an attempt to reduce sheet resistivity of the material used for the gate electrode in MOS devices, refractory metals or refractory silicides such as molybdenum, titanium disilicide, tantalum disilicide, and molybdenum disilicide have been considered for use as materials in the gate structures of MOS integrated circuit structures. Reports on these considerations have been presented by A. T. Sinha et al at the IEEE Reliability Physics Symposium, in April 1980, entitled "Generic MOS Reliability of the High
Conductivity TaSi2/n+ Poly-Si Gate Structure", and by S. P.Murarka, at the IEEE International Electron
Devices meeting in December, 1979, entitled "Refractory Silicides for Low Resistivity Gates and
Interconnects." Although the use of the materials proposed in these reports in MOS devices provides a reduction in sheet resistivity as compared to heavily- doped polysilicon, they are often difficult to deposit and to etch accurately, and often degrade the electrical characteristics of the MOS integrated circuits which include these materials in their gate structures by introducing additional deleterious mechanisms, such as instabilities, into the devices.
It is, therefore, an object of the invention to provide an MOS silicon gate device capable of operating at higher speeds than has thus far been possible.
It is a further object of the invention to provide an
MOS structure of the type described which can be fabricated without the need for additional photolithographic operations.
It is a further object of the invention to provide an improved conducting gate material which can be formed by the use of deposition and etching techniques, the characteristics of which are known and understood by MOS engineers.
It is a general object of the invention to provide an
MOS structure which provides the advantages of conventional silicon gate technology while providing a substantial reduction in sheet resistivity and a concomitant increase in device operating speed.
In accordance with the invention, a conductive layer of a metal or metal alloy is interposed or "sandwiched" between two layers to form a composite gate electrode of an MOS device. When the material of the intermediate layer is a metal, the sandwich is heated so that the metal in the intermediate layer reacts with the overlying and underlying polysilicon layers to form a silicide of the metal. The gate electrode structure fabricated in this manner, in which a conductive metal silicide is interposed between two polysilicon layers, has a significantly reduced sheet resistivity.
To the accomplishment of the above and any further objects that may hereinafter appear, the present invention relates to a silicon-gate MOS device and the method for its manufacture, substantially as defined in the appended claims, and as described in the following specification as considered together with the accompanying drawing in which:
Figure 1 is a cross section of an MOS device during an intermediate state of its fabrication in accordance with the present invention;
Figure 2 is a cross section of the MOS device of
Figure 1 at a later stage of its fabrication; and
Figure 3 is a cross section of the device at a still later stage of its fabrication.
In Figure 1,there is shown an MOS device afterthe completion of an early stage of its fabrication. As therein shown, a thin (typically 1 ,OOOÂ) insulating layer 10 of a silicon dioxide is formed in a conventional manner over a substrate 12 of silicon, here shown for purposes of illustration, as being of p-type conductivity.
A highly doped polycrystalline silicon layer 14 is deposited over the thin oxide layer 10. The thickness of this highly doped polycrystalline silicon layer is, typically, between 500 and 2,500A, and it is typically doped with n-type impurities such as arsenic or antimony. Next, a thin layer 16, which is advantageously between 500A and 1,500A in thickness, of a metal such as titanium, tantalum, tungsten, platinum or molybdenum is deposited over polysilicon layer 14. The material chosen for use in layer 16 is preferably a metal having the property of being able to combine with polysilicon at high temperatures to form a conducting silicide.The material of layer 16 may also be an alloy or compound of a metal, such as titanium disilicide, which has comparable characteristics, but does not need to further react with the polysilicon to form the silicide of the metal. In the embodiment of the invention herein described, the material of layer 16 is titanium which may be deposited onto polysilicon layer 14 by electronbeam evaporation.
Immediately following the deposition of the titanium layer 16, a second polysilicon layer 18, which may be doped with an n-type impurity such as arsenic, antimony, or phosphorus, is deposited over the titanium layer 16 in a conventional manner to a thickness in the order of 2,000A, after which a masking layer 20 of silicon nitride of a thickness in the order of 1,500 is deposited over the polysilicon layer using plasma deposition techniques at temperatures lower than 500 C.
Following the deposition of the nitride layer 20, a layer of photoresist material (not shown) is deposited over the multilayered structure and is thereafter exposed and developed to a desired pattern through the use of conventional photolithographic techniques. Next, using the patterned photoresist as a mask, the underlying silicon nitride layer 20 is etched through conventional chemical etching or plasma etching techniques and the remaining photo- resist is stripped off. Then, using the patterned layer of silicon nitride as a mask, the underlying layers of polysilicon, titanium, polysilicon and silicon dioxide are etched away, one or more at a time using conventional chemical etching, plasma etching, or ion-milling techniques, down to the silicon substrate 12. The structure that is achieved as a result of these steps is shown in Figure 1.When ion-milling techniques are employed, it may be desirable to subject the structure to high temperatures (which would result in the formation of the silicide) before the ion-milling procedure is performed.
The structure of Figure 1 is then subjected to a diffusion or implantation operation in which the multilayered structure of Figure 1 operates as a mask to achieve a self-aligned gate structure, whereby spaced n±type source and drain regions 22 and 24 are formed in the upper surface of substrate 12, as shown in Figure 2. During, or before, this operation, the structure is typically exposed to temperatures in excess of 7000C in an inert ambient such as dry nitrogen for a sufficient period of time to allow the metal of the intermediate layer 16, here titanium, to react with the polycrystalline silicon material directly above and below it to form a silicide of the metal, here titanium disilicide 26 (Figure 2).
In the event that titanium disilicide or other conductive disilicide or alloy of a metal is employed as the starting material for layer 16, no significant further reaction would occur between that material and the polysilicon layers, although the resulting structure would be comparable in that it would comprise the layer of conductive silicide covered by and overlying a polysilicon layer
The titanium disilicide layer 26 in the resulting "sandwich" gate electrode is advantageous as it behaves in a manner similar to a refractory metal, is highly conductive, and oxidizes at a rate comparable to the polysilicon.
Thereafter, the structure of Figure 2 is subjected to a local oxidation operation in which the silicon nitride layer 20 is used as a mask. In this operation, the silicon substrate 12 is oxidized so as to form a thick oxide layer 28 of a thickness in the order of 10,000 , which extends below and surrounds the composite conducting gate electrode. The side walls of the composite conducting material are also oxidized during this operation.
Thereafter, the silicon nitride layer 20 is removed resulting in the structure shown in Figure 3. The structure includes a three-layer composite gate electrode made up of the two polysilicon layers and the intermediate titanium disilicide layer. Preferably, an additional diffusion may be subsequently performed in the exposed upper (polysilicon) surface of the composite layer, and an additional oxidation step may be performed to the upper surface of the polysilicon layer, thereby to provide a thin oxide layer (not shown), which provides electrical isolation between the polysilicon layer and a subsequently formed, overlying metal interconnection layer (also not shown). Alternately, a similar, but thicker, oxide layer may be chemically deposited to provide such electrical isolation. The resulting MOS structure is then completed according to conventional fabrication techniques.
The MOS device constructed according to the present invention, as described in the foregoing exemplary embodiment, provides a low-sheet resistivity composite gate electrode which is substantially equivalent in all other ways to a conventional polysilicon gate electrode. The composite gate electrode of the invention includes a highly conductive metal silicide layer sandwiched between polysilicon layers. However, it differs from the conventional silicon-gate MOS device in that it provides a remarkably low value of sheet resistivity, in the order of between 0.5 and 5.0 ohms per square, as compared to conventional doped polysilicon gate structures in which the sheet resistivity of the doped polysilicon is typically between 15 and 40 ohms per square.The reduced sheet resistivity achieved in the MOS device of the present invention significantly improves the speed of the MOS device and is thus highly advantageous for use in many applications of MOS devices, such as random-access memories, in which speed of operation is of particular importance.
In addition, the gate-insulator interface between the first polysilicon layer 14 and the oxide layer 10is a polysilicon-8iO2 interface and all contacts made to the conductive gate will be to the upper polysilicon layer 18. Since the characteristics of the polysilicon
SiO2 gate-insulator interface and of the aluminum connections to the overlying polysilicon layer are known to the MOS process engineer, the improved gate electrode structure of the invention can be readily utilized by the manufacturer of MOS devices without the need for additional considerations.
Although the invention has been specifically described for purposes of example with titanium used as the starting material for the conductive layer interposed between the two polysilicon layers, other metals and alloys may also be used which meet the requirements for this material as set forth above. It will thus be appreciated that modifications may be made in the embodiment of the invention herein bove described without necessarily departing from the spirit and scoope of the invention.
Claims (15)
1. A method of fabricating an MOS device which comprises the steps of providing a substrate, forming on a surface of said substrate a thin insulating layer, depositing on said insulating layer a first layer of polysilicon, depositing on said first polysilicon layer an electrically conductive layer of a material capable of reacting with polysilicon when heated to an elevated temperature to form a conductive silicide, depositing a second polysilicon layer over said conductive layer, and thereafter heating said structure to cause polysilicon in said first and second polysilicon layers to react with the material of said conductive layer to form a silicide of the material of said conductive layer.
2. The method of Claim 1, in which said conductive layer is formed of a metal.
3. The method of Claim 2, in which said conductive layer is a metal selected from the group consisting of titanium, tantalum, tungsten, platinum, and molybdenum.
4. The method of Claim 1, further comprising the step of oxidizing said substrate to form a thick oxide layer which surrounds said conductive layer and said first and second polysilicon layers.
5. A method of fabricating an MOS device which comprises the steps of providing a silicon substrate, forming a thin oxide layer over said substrate, depositing a first doped polysilicon layer over said thin oxide layer, depositing a conductive layer over said first polysilicon layer, depositing a second doped polysilicon layer over said conductive layer, and selectively removing portions of said oxide layer, said conductive layer, and said first and second polysilicon layers, thereby to form a composite three-layer gate structure in which said conductive layer is interposed between said first and second polysilicon layers.
6. The method of Claim 5, in which said conductive layer is formed of a metal.
7. The method of Claim 5, in which said conductive layer is a metal selected from the group consisting of titanium, tantalum, tungsten, platinum, and molybdenum.
8. The method of Claim 6, further comprising the step of heating said gate structure in an inert ambient to cause said metal to react with the polysilicon of said first and second polysilicon layers to form a silicide of said metal.
9. The method of Claim 8, in which said conductive layer is a metal selected from the group consisting of titanium, tantalum, tungsten, platinum, and molybdenum.
10. The method of Claim 5, in which said conductive layer is formed of a metal silicide.
11. The method of Claim 5, further comprising the steps of oxidizing said substrate to form a thick oxide layer which surrounds said conductive layer and said first and second polysilicon layers.
12. An MOS transistor device comprising a substrate, spaced source and drain regions formed in a surface of said substrate, an oxide layer overlying said substrate surface and extending between said source and drain regions, and a gate electrode structure overlying said oxide layer, said gate electrode structure comprising a first doped polysilicon layer overlying said oxide layer, an electrically conductive layer overlying and in contact with said first polysilicon layer, and a second polysilicon layer overlying and in contact with said conductive layer.
13. The MOS device of Claim 12, in which said conductive layer is a silicide of a metal selected from the group consisting of titanium, tantalum, tungsten, platinum, and molybdenum.
14. A method of fabricating an MOS device, substantially as herein described with reference to the accompanying drawings.
15. An MOS device substantially as herein described with reference to the accompanying draw ings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15717680A | 1980-06-06 | 1980-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2077993A true GB2077993A (en) | 1981-12-23 |
Family
ID=22562636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8109247A Withdrawn GB2077993A (en) | 1980-06-06 | 1981-03-24 | Low sheet resistivity composite conductor gate MOS device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5713771A (en) |
| DE (1) | DE3122437A1 (en) |
| FR (1) | FR2484140A1 (en) |
| GB (1) | GB2077993A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0071029A2 (en) * | 1981-07-30 | 1983-02-09 | International Business Machines Corporation | Method for fabricating self-passivated composite silicon-silicide conductive electrodes |
| US4855245A (en) * | 1985-09-13 | 1989-08-08 | Siemens Aktiengesellschaft | Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate |
| US4870033A (en) * | 1985-03-19 | 1989-09-26 | Yamaha Corporation | Method of manufacturing a multilayer electrode containing silicide for a semiconductor device |
| US4874717A (en) * | 1982-08-12 | 1989-10-17 | Siemens Aktiengesellschaft | Semiconductor circuit containing integrated bipolar and MOS transistors on a chip and method of producing same |
| EP0339586A2 (en) * | 1988-04-25 | 1989-11-02 | Nec Corporation | Semiconductor device having improved gate capacitance and manufacturing method therefor |
| US4992391A (en) * | 1989-11-29 | 1991-02-12 | Advanced Micro Devices, Inc. | Process for fabricating a control gate for a floating gate FET |
| US5013686A (en) * | 1987-09-30 | 1991-05-07 | Samsung Electronics Co., Ltd. | Method of making semiconductor devices having ohmic contact |
| USRE35111E (en) * | 1989-05-31 | 1995-12-05 | Sgs-Thomson Microelectronics, Inc. | Local interconnect process for integrated circuits |
| US5518960A (en) * | 1993-03-26 | 1996-05-21 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a wiring layer including amorphous silicon and refractory metal silicide |
| US5661081A (en) * | 1994-09-30 | 1997-08-26 | United Microelectronics Corporation | Method of bonding an aluminum wire to an intergrated circuit bond pad |
| GB2344216A (en) * | 1998-11-26 | 2000-05-31 | Hyundai Electronics Ind | Forming gate electrodes |
| EP1005094A2 (en) * | 1998-11-25 | 2000-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor devices having a thin film field-effect transistor and corresponding manufacturing methods |
| US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
| US6284584B1 (en) | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
| US6387788B2 (en) * | 1998-06-29 | 2002-05-14 | Hyundai Electronics Industries Co., Ltd. | Method for forming polycide gate electrode of metal oxide semiconductor field effect transistor |
| US6869849B2 (en) * | 2000-10-25 | 2005-03-22 | Nec Electronics Corporation | Semiconductor device and its manufacturing method |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3211761A1 (en) * | 1982-03-30 | 1983-10-06 | Siemens Ag | METHOD FOR MANUFACTURING INTEGRATED MOS FIELD EFFECT TRANSISTOR CIRCUITS IN SILICON GATE TECHNOLOGY WITH SILICIDE-COVERED DIFFUSION AREAS AS LOW-RESISTANT CONDUCTORS |
| DE3304651A1 (en) * | 1983-02-10 | 1984-08-16 | Siemens AG, 1000 Berlin und 8000 München | DYNAMIC SEMICONDUCTOR MEMORY CELL WITH OPTIONAL ACCESS (DRAM) AND METHOD FOR THEIR PRODUCTION |
| JPS59195870A (en) * | 1983-04-21 | 1984-11-07 | Toshiba Corp | semiconductor equipment |
| JPS60132353A (en) * | 1983-12-20 | 1985-07-15 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
| JPS60182133A (en) * | 1984-02-29 | 1985-09-17 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS6362356A (en) * | 1986-09-03 | 1988-03-18 | Mitsubishi Electric Corp | Semiconductor device |
| JP2515574Y2 (en) * | 1988-11-22 | 1996-10-30 | 株式会社三協精機製作所 | Smoke backflow prevention damper |
-
1981
- 1981-03-24 GB GB8109247A patent/GB2077993A/en not_active Withdrawn
- 1981-04-17 FR FR8107798A patent/FR2484140A1/en active Pending
- 1981-04-21 JP JP6055881A patent/JPS5713771A/en active Pending
- 1981-06-05 DE DE19813122437 patent/DE3122437A1/en not_active Withdrawn
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0071029A2 (en) * | 1981-07-30 | 1983-02-09 | International Business Machines Corporation | Method for fabricating self-passivated composite silicon-silicide conductive electrodes |
| EP0071029A3 (en) * | 1981-07-30 | 1984-12-27 | International Business Machines Corporation | Method for fabricating self-passivated composite silicon-silicide conductive electrodes |
| US4874717A (en) * | 1982-08-12 | 1989-10-17 | Siemens Aktiengesellschaft | Semiconductor circuit containing integrated bipolar and MOS transistors on a chip and method of producing same |
| US4870033A (en) * | 1985-03-19 | 1989-09-26 | Yamaha Corporation | Method of manufacturing a multilayer electrode containing silicide for a semiconductor device |
| US4855245A (en) * | 1985-09-13 | 1989-08-08 | Siemens Aktiengesellschaft | Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate |
| US5013686A (en) * | 1987-09-30 | 1991-05-07 | Samsung Electronics Co., Ltd. | Method of making semiconductor devices having ohmic contact |
| EP0339586A2 (en) * | 1988-04-25 | 1989-11-02 | Nec Corporation | Semiconductor device having improved gate capacitance and manufacturing method therefor |
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Also Published As
| Publication number | Publication date |
|---|---|
| DE3122437A1 (en) | 1982-06-03 |
| FR2484140A1 (en) | 1981-12-11 |
| JPS5713771A (en) | 1982-01-23 |
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