GB2076614A - Methods and apparatus for digitally signalling sounds and tones in a pcm multiplex system - Google Patents

Description

1 GB 2 076 614 A 1

SPECIFICATION Methods and apparatus for digitally signalling sounds and tones in a PCM multiplex system

This invention relates to time multiplex PCM (pulse code modulation) communication systems.

The following are considered to constitute the most relevant items of prior art:

Ref. 1: United States Patent 3,706,855 issued December 1 9th, 1972.

Ref. 2: -Multifrequency (MF) Tone-Generating System For a Pulse-CodeModulation (PCM) Digital Exchange- by S.G. Pitroda, lEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, VOL. COM-1 9, No. 5, pages 588-596, October 197 1.

Ref. 3: 'Migital Concepts in Service Circuits- by S.G. Pitroda, GTE AUTOMATIC ELECTRIC TECHNICAL JOURNAL, pages 315-322, April 1973.

Ref. 4: -Progress Tones in PCM Switching Equipment- by Pitroda and Lindsay, IEEE TRANSACTIONS ON COMMUNICATIONS, pages 1431-1434, December 1973.

Ref. 5: Products of Wescom Switching, Inc. (Downers Grove, Illinois) known as Model 5888, Digital Tone Generator, and Model 5889, Digital Generator Control.

The five identified references, and perhaps others not known to applicants, confirm that it has 15 been known to those skilled in the art that sounds (sometimes called tones) formed by one, two or more sine waves of predetermined frequencies can be produced in PCM systems without actually creating and mixing the analog sine wave signals and then sampling to convert them to PAM (pulse amplitude modulation) form followed by digital-to-analog conversion into PCM samples, Instead, the successive samples (usually taken on the multi-frequency analog wave at an 8 KHz. sampling rate) may be determined once and stored as separate words in suitable memory, a ROM (read-only memory) being sufficient. In the past, a separate ROM has been provided for each multi- frequency tone, and the sample words have been read out simultaneously from all ROM's with sequential scanning, one word per frame being read out and available during essentially the entire frame. To "switch" a tone to a desired destination in a switching network, the output of that tone's ROM was sent into the switching network in one network time slot and connected to the appropriate outgoing channel in the network.

It has also been known to create not only steady or continuous sounds or tones, but also to give certain progress tones predetermined on/off duty cycles. For example, the familiar "busy signal" in telephone systems is commonly a "sound" representable as a combination of 480 Hz. and 620 Hz. sine waves but interrupted so that it is alternately "on" for 0.5 second and "off" for 0.5 second. In the prior 30 art, an on/off timer has been provided for each distinctive on/off type tone, and associated with the ROM memory holding the PCM samples for the sound to be turned on and off.

As indicated, the present invention relates in general to time multiplex PCIVI (pulse code modulation) communication systems and is ideally suited, but not restricted, to those of the type employing digital switching. More particularly, the invention relates to sources of sounds and tones, and 35 to methods of creating such sounds and tones, used in such systems and formed by previously established and stored sets of PCM samples, without actually creating multi-frequency analog waves, PAM sampling or repeated synchronous PCM encoding.

It is the general aim of the present invention to provide methods and apparatus for generating any one of a large plurality of tones in any one of many time slots (channels) of the repetitive cycles (frames) 40 in a PCM time multiplex communication system in a fashion that a single hardware assembly, manufacturable as a single printed circuit board, carries out the method steps to so produce signals digitally representing the desired tones in the desired time slots. This overcomes the prior practice of dedicating considerable hardware to the job of generating each one of many tones and makes possible the realization of all tone requirements for a central installation (PBX or central office) by apparatus which is less bulky, greatly reduced in cost and which reduces the procedures for switching tones into desired time slots.

It is a coordinate object of the invention to do away with the prior practice of making a digital sample of each of many tones available as a multi-bit word signal during essentially the entire time interval of each multi-channel cycle and switching such word signal into a desired time slot. In contrast, 5() the present invention achieves economy of hardware and efficiency in operational steps by creating a multi-bit signal representing in PCM form a tone sample only during the relatively short time slot of each cycle when such multi-bit signal is needed.

Another important object of the invention is to provide almost unlimited combinations of "sounds" with on/off "schedules" to provide availability of a great number of digitally signaled "tones" in a PCM 55 time multiplex system. For example, any one of a plurality of sounds SD,,... SD, may be combined with any one of a plurality of schedules SCH.... SCHn to provide one of the tones TN,, the quantity Q of available tones being theoretically equal to X-Y, where X represents the number of sounds and Y represents the number of schedules. In a related aspect, the invention makes it simple and easy to change tones by assigning to them changed combinations of sounds and schedules merely by changing 60 low-cost ROM's holding different stored data or by writing different data into RAM's or PROM's if the latter are originally employed.

Still another object is to provide methods and apparatus by which simple commands received asynchronously from a central control unit result in the outputting of any desired one of many tones in 2 GB 2 076 614 A 2 any desired one of the several time slots within recurring cycles or frames. But a related and advantageous object, in a preferred form of the invention, is to provide a predetermined selection of certain "fixed tones" which are always and invariably outputted in preassigned time slots of every cycle, with tones being selectively switchable into the remainder of the time slots.

It is also an object here to output successive PCM samples of a sound in the same time slot of successive cycles (frames), where a limited number of samples for the sound are stored in a main memory for scanning, and with the advantage that each scan may differ from the previous one by virtue of apparatus and a procedure for generating the "next sample address" from the nature of the "present sample address". This advantage is achieved through the use of common hardware for all of the sounds which are being respectively transmitted in the plural channels or time slots.

As a corollary to the foregoing, it is an object of the invention to simplify hardware and facilitate operational procedures for scanning a plurality of digital sound samples held in main memory at successive address locations by applying, during one time slot of one cycle, address signals read out of a certain location of a next-sample read/write memory; thereafter writing into that certain location new signals which are incremented or decremented by one in relation to those previously existing, and reading out the new address signals during the same time slot of the ensuing cycle.

An ancillary object of the invention is to simplify apparatus and operating procedures for digital signaling of sounds by storing the successive digital samples of each of a plurality of sounds in separate blocks of addressable main memory with the last sample for each sound at an address numerically representable as a multiple of sound constant (such as 256) with the resulting advantage that as the 20 samples are read one at a time with scanning, the reaching of the last sample for any sound is easily detached from the presence of the same predetermined combination of 1's and O's in lower order places of the address signals applied to the main memory.

A related object of the invention is to simplify and make possible successive scanning of samples in each of a plurality of sets of samples stored in a main memory by initially storing in an auxiliary "first 25 sample" memory the address location of the first sample for each set, whereby jumping to the first sample to start a new scan or detecting the reaching of the first sample at the end of a scan is easily accomplished.

Still another object of the invention is to control the sequence of successive scans of sets of digital samples representing various ones of a plurality of sounds, different sets having different characteristic 30 scan sequence requirements, by initially storing for each sound a "sequence characteristic" word, and reading from such storage such characteristic word each time a sample is being outputted from the corresponding set, in order to determine, in part, the address of the next sample to be outputted from that set. This enables each of the plural "sounds", which is represented by one set of samples stored in main memory, to have any of the characteristics of (a) last sample repeat or no last sample repeat, (b) scan order reversal or no scan order reversal, and (c) alternate scan sign charge or no alternate scan sign change depending upon the shape of a symmetrical portion of the cyclic analog wave which is represented digitally by the stored set of samples.

As a special advantage, the present invention provides easily implemented methods and apparatus for producing digital signals representing "intercept" tones, i. e. tones which when converted 40 to audible form appear as first and second sounds alternating with a predetermined duty cycle wherein the first and second sounds may be chosen as those represented by stored sample sets in the main memory.

And yet another object of the invention is to provide a final gate control signal which can be given any one of a plurality of on/off duty cycles (including continuously on or continuously off) without separate timer circuits or complex logic the apparatus and methods involving storing of on/off schedules in a common memory and reading the words of such memory in a timed rollover sequence.

Other objects and advantages will become apparent as the following description proceeds, taken in conjunction with the Tables I-XII which are located for convenient reference at the end of this specification, and in conjunction with the accompanying drawings.

Figure 1 is a generalized block diagram of a portion of an exemplary PCM time multiplex communication system, illustrating by way of background the incorporation therein of a digital tone source embodying the present invention; Figures 2A and 213, when joined, form a block diagram illustrating apparatus constituting an exemplary preferred embodiment of the digital tone source, and which operates to carry out the 55 methods of the present invention; Figure 3 is a diagram illustrating inner details of a portion of the tone pattern TP ROM which appears in Figure 213; Figure 4 is a block diagram showing certain details of the timing circuits which appear more generally in Figure 2A; 2B; Figure 5 is a more detailed illustration of the---LogicA- portion of the apparatus shown in Figure Figures 6A and 6B, when joined end-to-end form a diagram which illustrates the wave forms and the relative timing of various signals which are created and utilized, over the span of one cycle orframe, 3 GB 2 076 614 A 3 in the operation of the apparatus shown in Figures 2A, 213 to practice the methods of the invention in one preferred form; Figure 7 is a timing chart which shows how certain signals change over the span of two adjacent time slots within a typical cycle, and which aids in understanding the methods of the present invention; 5 and Figures 8A-8E are illustrations of arbitrarily chosen examples of different types of cyclic analog waves which have different scan sequence requirements for the PCM samples thereof.

While the invention has been shown and will be described with reference to specific, exemplary embodiments of methods and apparatus, there is no intention that it thus be limited to the particular aspects of details of such embodiments. On the contrary, it is intended here to cover all modifications, 10 alternatives, equivalents and su b- combi nations which fall within the spirit and scope of the invention as defined in the appended claims.

A. Definitions and Symbols It will be useful to set out generally the definitions of certain terms employed in this specification.

"Sound" means the audibly perceivable sensation to the ear, in pitch, produced by a cyclically recurring analog wave (when converted by a transducer into sound waves) constituted by one, two or more mixed sine waves of predetermined frequencies. In the present exemplary description, reference will be made to a plurality of sounds SD. through SN, where "n" is arbitrarily chosen as thirty-one. For example, the "busy tone" sound in a typical telephone system is a combination of the two sine waves having frequencies of 480 and 620 Hz.

"Schedule" means the on/off duty cycle imparted to any sound. In the present case reference will 20 be made to a plurality of possible schedules SCH6--SCHn, where "n" is arbitrarily chosen as fifteen. As an example, the schedule SCH3 might be 0.3 seconds on and 0.2 seconds off for an all trunk busy tone.

The schedules may include one which is continuously on and one which is continuously off (in the latter case, no sound or tone actually being transmitted so the "quiet tone" is formed).

"Tone" means the combination of any sound with any schedule. In practice, the impression as 25 perceived by the ear of a listener is distinct for each tone and readily recognizable. If there are thirty two possible sounds and sixteen possible schedules, then there are 32 x 16 = 512 theoretically possible tones, but of course, all such tones do not have to be employed. In the embodiment to be described, there are a plurality of possible tones TN.... TNn where "n" is arbitrarily chosen to be fortyseven.

"Time slot" denotes each of the successive channel intervals within recurring cycles or frames in a time multiplex system. Typical voice telephone PCM multiplex systems measure off successive cycles or frames of 125,u. sec. duration, with one hundred ninety-three time slots of.648 /t sec. in each cycle to form one hundred ninety-two voice channels plus a framing channel. At a lower order level of multiplexing, however, a cycle of 125 y sec. may be divided into ninety-six time slots or channels each 35 1.3 p sec. in duration, plus a period of.648 It sec. for synchronizing. With regard to the exemplary embodiment of a tone source here to be described, forty- eight of those ninety-six time slots are used to carry different desired ones of a large plurality of tones, and thus insofar as the tone source is concerned, it may be viewed as measuring off forty-eight time slots, assigned to tones, in each repetitive cycle of 125 y sec., with each time slot occupying 1.3 JU sec.

"Cycle" as here used is synonymous with "frame" as the latter term is employed in the telephony art, and means the period spanned by all time slots of a multi-channel time multiplexed signal. Each time slot recurs at the cycle rate.

"Fixed tone" means a tone which is transmitted digitally as PCM samples, with successive samples being always transmitted in the same time slot of every cycle (except, of course during off 45 intervals of the tone schedule). In effect, a channel or time slot is permanently dedicated to each "fixed tone".

"Switched tone" means a tone which, time-wise, is selectively switched for transmission in any desired time slot of successive cycles. The tone can be taken out of that time slot and replaced with another tone in response to command signals from a central call processing control unit.

"Sample " means a multi-bit binary word which represents numerically, according to the chosen code for PCM, the magnitude and polarity of a point on a fictitious analog wave which audibly would produce a given sound. A sample is the multi-bit word which would result if the wave were sampled to produce a PAM pulse and the latter then converted from analog into digital pulse code form, although in the practice of the present invention such samples are preformed and initially stored as separate words (usually of eight bits, seven representing numerically the magnitude and the eighth representing the sign) in a mufti-word addressable. readable memory.

"Pattern" or "set" means a plurality of samples which represent the successive magnitudes of a symmetrical portion of a cyclically repeating analog sound wave, assuming that the latter were sampled at a fixed rate, typically 8 KHz. Because symmetry will exist in most multi-frequency sound waves, a 60 limited number of samples may be repeatedly used with repeated scanning to continuously signal the sound in PCM form.

4 GB 2 076 614 A 4 ---Scan"means to take and output the samples of a pattern in succession (either in forward or reverse order) until all samples have been used (and after which another scan may begin). In some scans, the last sample is used twice.

---Scansequence- means the succession in which scans of different types are made through the samples of a set to produce successive output signals which, in digital form, represent the corresponding sound. Depending upon the symmetry of the analog wave, the scan sequence may involve using all samples repeatedly in first-to-last order, using all samples in scans which proceed alternately in first-to-last and last-to-first order, using all samples in scans wherein the signs of the output signals are complemented during alternate scans, or using all samples in successive scans, with 10 the last sample being repeated in certain ones of the scans.

B. A Typical Background Environment of the Invention

Referring now to Figure 1, one known PCM mutliplex communication system typically includes, as a portion thereof, one hundred ninety-two voice inlet ports P,7-%,, whose analog voice waves are, in effect, to be transmitted to a digital switching network 10 on an eight-conductor bus 11 time-shared to carry corresponding PCM signals in one hundred ninety-two channels or time slots within repetitive 1 cycles of 125 lu sec. Each time slot is typically.648 p sec. long, the 1 93rd time slot being used for synchronization. Within the digital switching network, selective -connections- are made to route any incoming channel signal to a desired channel of an outgoing time-shared bus (not shown), so that twoway communication may be established between any two telephone sets served by the system, the outgoing signals being decoded to PAM format and reconverted to analog form before reaching a receiving telephone. The details of the digital switching network are known to those skilled in the art, and need noo be described. It is also known in the art how a call processing unit 12 is constructed to supply the necessary control signals, via a bus 14, to make the network put up and take down connections.

In an ordinary, all voice setup, the entry ports Pd--Pl., are treated in groups of twenty-four P6_P2.1 25 P247_P4, and so on in order to time-share eight analog-to-digital (A/D) converters 1 56--l 5, Taking ports Pd_P2, as an example, multiplex sampling circuits 18 are timed by signals from a clock 16 such that the signal at each port is sampled at a rate of 8 KHz., with each sample being converted into a PAM voltage, twenty-four such voltages being fed in each repetitive cycle via a conductor 19 to A/D converter 150 whose output is a succession of eight-bit digital samples on a twenty-four channel bus 30 The sampling circuits are so timed that the outputs of the first four A/D converters 15. to 153 are sequentially staggered in time, thereby forming in effect ninety-six channels in a cycle of 125 p sec., each channel occupying 1.3,u sec. The sampling of signals arriving at ports P96 to P1.1 is carried out in the same fashion with regard to the last four A/D converters 154 to 157' To further compress in time the one hundred ninety-two voice signals, the outputs of the eight A/D 35 converters are fed into first and second sections 22a, 22b of a first order multiplexer 22 which is timed by signals from the clock 16. In a fashion known in the art, the ninety- six PCM signals (each eight bits wide) on the output lines 206-20, are fed in sequence over a single conductor 24 each channel occupying a time slot It sec. wide with eight time-serial bits therein occurring at a rate of 162 nanoseconds per bit. Similarly, the PCM samples from converters 154 to 157 are serialized into ninety- 40 six channels on a line 25. The two lines 24 and 25 form inputs to a second order multiplexer 26 also timed by signals from the clock 16. In the second order multiplexer, the two 96 channel serial signals are converted into one hundred ninety-two sequential channels or time slots (plus a 1 93rd time slot for synchronizing) each.648 It sec. long with eight bits of data appearing on the eight-conductor bus 11, forming one hundred ninety-two channels of input signals (corresponding to ports PO-P,,,) to the switching network 10.

It is beyond the necessary scope of this disclosure to describe the switching network 10, but those skilled in the art will fully understand that a cross connection of any incoming channel to an outgoing channel may be made, the conductors for the outgoing signals, and the components for demultiplexing, D/A converting back to PAM format, and reconverting into analog waves not here being illustrated. 50 GB 2 076 614 A 5 FREQUENCIES SCHED. (Seconds) TONENAME (Hz.) ON OFF Ring Back 0 1 440 &480 2 4 Ring Back 02 440 &480 2 4 Ring Back 03 440 &480 2 4 5 Busy 480 &620 0.5 0.5 All Trunk Busy 480 &620 0.3 0.2 Camp On 350 Continuous on Call Waiting 350 0.05 1.95 Night Call Waiting 350 0.05 0.45 10 Executive Call Waiting 350 0.05 0.95 Assurance 620 Continuous on Entry 480 Continuous on Quiet Continuous off Test 1020 Continuous on 15 Dial 350 &440 Continuous on Transfer Dial 350 &40 0.05 0.45 Distinctive Dial 440 Continuous on DTMF Digit 1 700 &900 Continuous on DTMF Digit 2 700 &1100 Continuous on 20 DTMF Digit 9 1100 &1500 Continuous on DTMF Digit 0 1300 &1500 Continuous on A full listing of IVIF tones for "tone" dialing is given in Ref. 1 identified above, with an explanation of how a symmetrical quarter of a full cycle of the analog wave for a given tone may be stored in the form of samples. The list here set forth is intended only to be representative and to show that a large number of 25 tones must be generated and made available in a modern PCM telephone system.

C. Introduction to the Invention

In keeping with the practice of the invention and the realization of its advantages, a single and structurally simple tone source 30 is provided to create digital signals for all of the tones which may be required or desired in a PCM multiplex communication system. It supplies both fixed and switched tones 30 and enables the available tones to be easily selected or changed.

As shown in Figure 1, certain ports P6-P,, are pre-empted and not used, the corresponding portion of the sampling circuits 18 thus being omitted, and the A/D converters 1 5,-l 51 being removed. This is the significance of the latter being drawn in dotted lines in Figure 1. The tone source 30 has an eight-conductor output bus OB feeding into the first order multiplexer section 22a to provide 35 tones in forty-eight channels of the one hundred ninety-two channels for the network 10. By connections set up in the network, the tone appearing in any of those forty-eight channels may be connected back out to any desired destination (the output path including, as is well known, conversion to analog waves accepted by a telephone earphone or loud speaker). Of course, the illustrated choice of preempting ports 0-47 and replacing them with the tone source 30 is arbitrary; a different quantity 40 and a different combination of the ports may be so chosen to be preempted for tones.

As indicated in Figure 1, the tone source 30 is synchronized in its operation by timing signals from the clock 16 and receives commands from the control unit via a command bus CB in order to be 6 GB 2 076 614 A 6 synchronized and switch different tones into different time slots. It is to be observed that in the exemplary system here illustrated, the tone source actually supplies PCM signals in forty-eight of the ninety-six time slots within each 125 y sec. cycle of the signals on conductor 24. Because of time staggering of the A/D converters 151-153 (if all four were in fact used), such that the signals from the ports are taken in P01 P241 P481 P72, P1, P25, P491 P73', order, the tones show up sequentially in the time slots TSO, TS, TS., TS6, TS, TS,0.. . TS.2, TS.3 of the successive time slots TS6--TS9. for each cycle on conductor 24.

D. The Structure and the Methods of a Preferred Embodiment of the Tone Source Referring next to Figures 2A and 2B, there is shown a main tone pattern memory labelled TP ROM10 and comprised of eight read-only memory chips CHPO_C'P7 each of which may be configured as containing 1024 words (addresses 0-1023) each eight bits wide. While erasable, reprogrammable PROM or readable/writable RAM memory units may be used, read-only memory ROM will suffice for the main memory because once "burned in" or stored, the contents consisting of patterns for a plurality of sounds rarely, if ever, need to be changed. Even then, changes are easily accomplished by substitution 15 of one or more new ROM chips.

The main memory TP ROM is set up initially by storing therein patterns or sets of samples for at least a symmetrical portion recurring cyclic analog waves which, if converted into sound, will produce corresponding sounds. In the present embodiment, thirty-two patterns PT6- PT,l for thirty-two such sounds SD6-SD,, are so stored, with the successive samples within each pattern or set in adjacent 20 address locations. Specifically, as indicated in Figure 213, each of the chips CHPO-CHP, stores four patterns. Because each chip contains 1024 word locations, there are a total of 8192 word locations, and thus any sample may be read-out by a unique address applied to an address bus and containing thirteen binary bits. Purely as a matter of choice in the present instance, however, each of the chips CHP,7-CHP, has in common ten address lines A6--A, formed into a bus, plus a chip read enable or chip 25 select terminal (here labelled CS0-CS1). The combination of 1's and O's and address lines A6--A.

selects one of the 1024 words of each chip, and an enabling signal to one of the chip select terminals CS0_CS7 selects one of the chips so that the stored sample at any single word location may be read out to the common eight-line output bus B of the TP ROM.

As is known in the art reflected by the above-identified prior art references, different sounds 30 require different numbers of digital samples. Some sounds may be signalled digitally by scanning through as few as twenty-one samples, and others may require, for example, one hundred one or one hundred seventeen samples. We have found that of the sounds to be digitally signalled from a practical, commercial embodiment of the invention, none requires more than two hundred fifty-six samples. In keeping with one feature of the the present invention, each sound pattern, regardless of the quantity of 35 samples therein, is stored in a block of memory words such that the last sample address for any pattern is recognizable by a common characteristic of the multi-bit address word applied to the TP ROM address lines. Figure 3 makes this clear by way of arbitrary exampoles Chips CHPO and CHP1 of the TP ROM are shown as each constituted by four blocks of words with two hundred fifty-six words in each block, i.e., block BLKO is formed by address locations 0-255, BLK, is formed by address locations 40 256-511, BLK2 is formed by address locations 512-767, and BLK3 is formed by locations 768-1023. Sound pattern PT, having twenty samples, is stored at locations 236-255; pattern PT1, having one hundred samples, is stored at locations 412-511; pattern PT2,having one hundred twenty samples, is stored at locations 648-767; and pattern PT, having fifty samples is stored at locations 974-1023. For this example, it will be seen that the last sample of every pattern resides at a location 45 addressable as a binary multiple of 256 (i.e., 255, 511, 767, 1023) and when the eight least significant bits of a ten bit address signal are detected as being all 1's, it is known that the last sample of a pattern is being read out to the bus B. Such detection is easily accomplished in a manner and for a purpose to be explained below.

The illustration of chip CHP, in Figure 3 conforms to the specific example of chip CHPO, but is more 50 generalized. It shows that for any of the sound patterns PT4--PT7 stored, the last sample address LSA is 255, 511, 767 or 1023, i.e. identifiable by a common characteristic of lower order bits A6--A7 in a multi-bit address signal on lines AC-Ag. The first sample address FSA of any pattern therefore depends upon the quantity of samples in the pattern, but in any event is readily determinable at the time data is initially stored in the TP ROM.

Referring momentarily to Figures 8A and 813, the analog waves there shown are typical for various sounds. The successive samples, and their signs, are represented by the vertical lines spaced at 125,u sec. intervals (a sampling rate of 8 KHz.). The sound for Figure 8A is thus representable by twenty-four samples which need to be scanned from left to right repeatedly. The sample on the extreme left (zero) is the first sample FS and that on the extreme right is the last sample LS. They are stored in 60 that order in numerically ascending address locations of a TP ROM block, with the last sample at one of the "common address bit" locations. In Figure 813, the wave is a single frequency sinusoid, so that fourteen samples suffice. These may be scanned successively from first-to- last, and then scanned repeatedly with the signs reversed during alternate scans. But in any case, the first sample is usually 7 GB 2 076 614 A 7 (although not necessarily) chosen at a zero crossing of the cyclic analog wave, the last sample is chosen at or near a subsequent zero crossing, with the samples of any set being stored in the main readable memory such that the last sample is at a -common binary multiple" address location and the first sample failing where it will at a known first sample address location FSA. Of course, it is within the purview of the invention to store the samples of each set in reverse order of a normal scan, i.e., to store the last sample of a pattern at the lowest address location of its block and the first sample at the highest used location within the block; a normal scan would proceed in numerically descending address order from the location of the first sample to that of the last sample, the last sample address being readily detectable by decoding of the ninth and tenth bits of a ten bit address word when the least significant 10 eight bits are all O's.

1. Producing Control Signals Identifying Time Slots With the contents and format of the TP ROM in mind, it may now be explained that the practice of the present invention includes creating control signals which exist during and uniquely identify each of a succession of time slots during successive cycles. The "time slots" here referred to, however, are those in which the tone source is active, and in the example of Figure 1 correspond to those which would 15 ordinarily be employed to carry signals from ports P0-p47. Thus, alternate pairs of the ninety-six time slots in one 125 p sec. cycle on line 24 form the plurality of tone source time slots which will here be designated as TSd-JS17. To produce the corresponding control signals Ud- CT4, in sequence, a sixstage binary counter 35 (Figure 2A) is driven by a signal CRCK produced by timing circuits 36 driven with a clock signal CLK. The counter counts up in response to a positive- going transition (rising edge) in 20 the bi-level signal CRCK applied to its count terminal Ct and is cleared to a zero state when and so long as its clear terminal CLR is held at a " 1 " level by an applied bi-level reset signal RST.

At this point, it will be helpful to indicate that the drawings in this case have been prepared with certain assumptions or conventions to simplify understanding of the apparatus, but which need not be -25 adopted in actual commercial products. First, bi-level voltages are assumed to represent a binary " 1 25 or "0" when at a relatively high or low level. Secondly, an component is assumed to respond or be enabled only when an input signal applied thereto is at a---1 " level, except for those input terminals labelled with the symbol in which case response occurs to the positive- going wave front or edge.

Of course, contrary cotiventions may be used in actual practice provided corresponding changes are made in logic elements such as AND, OR, NAND, NOR circuits such changes being readily made as a 30 matter of choice between available equivalents by those skilled in the art. Further, the inverted form or complement of any signal is here designated as an asterisk in the symbol for such signal instead of the more conventional bar. That is, the complement CLK of a signal CLK is represented by the symbol CLK.

To understand the operation of the counter 35 reference should first be made to the timing circuits 36 as they are set out in detail by Figure 4 and supplemented by the waveforms shown in Figures 6A 35 and 6B. First, it is to be noted that the timing circuits receive from the clock 16 of Figure 1 a squarewave clock signal CLK which forms the basic timing for the entire system. The CLK signal has a fixed period T which for concreteness in subsequent description will be assumed to be equal to.648 p see. Moreover, the control unit 12 and the multiplexing sampling circuits 18 (Figure 1) create a synchronizing signal SYNC which recurs at the frame rate of once per 125 iu sec. to lock all parts of the system together. As 40 shown in Figure 4, when the SYNC pulse arrives (see Figure 6A) it serves to preset the A stage of an eight place binary shift register R1 (the latter normally being cleared when SYNC arrives) which is shifted in response to positive wave fronts of the CLK signal. Thus, as indicated in Figure 6A in connection with the signal QD1, the outputs A and B are respectively high for the two successive periods T following the CLK wave front which first appears in coincidence with the SYNC signal. In the third 45 period T, the signal RST at the C terminal of register R 'I is high so that a reset pulse occurs every p sec. and synchronized with CLK each time the SYNC arrives. This starts a cycle of the tone source because the reset signal RST clears the counter 35 as shown in Figure 2A and simultaneously clears a second shift register R2 (Figure 4).

As the---1 " at terminal C of register R1 gets shifted to the D terminal, the signal QD1 (see Figure 50 6A) swings high for one clock period T and passes through an OR circuit 38 (Figure 4) to the preset terminal P R2 of the second eight-place binary shift register R2. The next rising edge of CLK therefore sets the A terminal of register R 'I to a 1 level, that '1---being thereafter repeatedly shifted and recycled through such register by each succeeding rising edge of the clock signal CLK. Thus, as shown in Figure 6A, the signal Q,, goes high for one period T following the elapsing of three periods T after the signal 55 RST ends; two periods T thereafter the terminal Q,, goes high for one period T; and two periods thereafter the terminal QH2 goes high for one period. The signal Q,,, flows through OR circuit 38 to make signal PR2 high, so that on the next positive edge of CLK, the A stage of register R2 is again set. Thus, after a reset pulse appears, the signals Q,, and Q.2 each recur with a time spacing of 8T and are relatively phased apart by 2T, as the waveforms of Figure 6A indicate.

To signal the existence of the tone slots (which comprise 48 out of 96 in a 125 p sec. cycle) that come in pairs, a tone slot signal TONS is formed by an OR circuit 39 fed with the signals QC2 and QE2 This signal TONS is applied to the preset terminal of a D-type flip-flop 40 to hold the latter in its " 1 state (and the signal CRCK at the " 1 " level) so long as TONS is present. When TONS is at a 0 level, 8 GB 2 076 614 A 8 however, the flip-flop 40 is clocked back to, or left in, the -0- state in response to a rising edge in the signal CLK produced from CLK by an inverter 41. Each time the signal TONS appears, the signal CRCK is driven high and the latter is driven low again when the next positive edge of CLK arrives following the return of TONS to a -0- level. The complement signal CRCK is formed at the U terminal of flip-flop 5 40.

As shown in Figure 6A, the signal CRCK thus has the form of two---1 " level intervals separated by approximately 1/2 T, such pairs of intervals recurring with a time spacing of 8T. Since the counter 35 (Figure 2A) responds to the rising edges in the signal CRCK, it thus signals in binary notation on six output lines (LSB on the right) a number which increments by one essentially at the instant of the negative-going edges in the signal CRCK. This is illustrated in Figures 6A and 6B by the line labelled CT 10 STATE., which shows the counter 35 being cleared to the zero state by the signal RST and thereafter incrementing to count states 1, 2, 3, 4 and so on. The counter will ultimately reach the state of fortyeight before being again cleared by the RST pulse which appears at the beginning of the next cycle.

The six bit output of the counter 35 thus forms control signals CT,,--CT, which sequentially change from 0-47 and uniquely identify the successive tone sl6ts TSO... TS47 within each cycle of ninety-six time slots. Those signals are applied to the B input of a 2:1 multiplexer 42 which passes them to its output except when the signal FIST is high. It may be noted in Figure 6A, that the tone time slots are each 2T wide. Odd-numbered tone slots are coincident with the counter 35 residing in count states 1,3,5... 47; but even numbered tone slots are, in effect, located in time during the terminal portions of the intervals during which the counter is count states 0, 2, 4 46. This comes about because the 20 counter increments to an even numbered count state at the end of an odd numbered tone slot, remains in that state during two voice channel slots (carrying signals from A/D converters 15, and 15, in Figure 1), the last 2T interval of an even count state constituting an even numbered tone slot.

2. A Typical Cycle In keeping with the next step according to the present invention, the control signals CT6--CT, 25 which increment through values of 0-47 are caused to effect readout from the TP ROM, during each tone time slot TSC-TS47, one sample of the pattern for that one of the sound SD,7--SD,, preselected for transmission in that particular slot.

A particular sound pattern is selected for each of the tone time slots TS, -TS47 by a six-bit signal TT 0-5 which may have any of forty-eight numerical values during each slot. As will be explained 30 below, the signal TT 0-5 changes from slot to slot to identify one tone TN,, to be transmitted in a given time slot TSY, the tone TN,, being one of a possible forty-eight tones TN6--TN47 (each tone being made up by one of the sounds SD6--SD,, and one of the schedules SCH6--SCH,,). That signal RR 0-5 is applied as an address for reading of two memories 44 and 45 here shown as a Pattern Select ROM and a Schedule Select ROM. The latter will be treated hereinafter; the former is simply a 48 x 6 ROM which 35 is initially constructed to store in its forty-eight locations five bit words which numerically identify one of the sound patterns PT6--PT,,. The sixth bit b5 of each word in the memory 44 (and which when readout is signalled on a conductor PA5) is used for a special purpose to be explained later, and may be ignored for the present. Thus, each word which is stored in the memory 44 can represent numerically a value of 0-31, and when readout onto the memory output lines will call for or "select" one of the patterns PT6--PT,,, as will become clear. When a particular time slot TS, arrives, the signals TT 0-5 will represent a tone TN. (one of a possible forty-eight) and thus will cause readout from pattern select TOM 44 signals PA 0-4 which represent a particular pattern PT,. (one of a possible thirty-two) which is the sound portion of the tone TN, To put this in terms of a concrete example, let it be assumed that the busy tone (see the tone listing set out above) is assigned tone No. 11 and that the sound pattern for 480 45 Hz. plus 620 Hz. is assigned pattern No. 17; and that it is desired to transmit the busy tone in tone time slot No. 23. For such assumed facts:

(a) The pattern of samples for the busy sound would be initially stored in block BLK, of TP ROM chip CHP41 with its last sample at the address 511 on the chip, and its first sample thus at a known lower-numbered address on that chip.

(b) The number -17" would initially be stored in binary form as bits b.b4 at the address 11 in the pattern select memory 4.

(c) Then, during operation of the tone source, and as explained more fully below, the signals TT 0-5 would be created to represent the value -11 " during that interval when the control signals CT 0-5 represent the number "23" and thus when tone time slot TS23 occurs in each of successive cycles. 55 (d) When time slot TS23 arrives, therefore, the output of memory 44 (from address 11) on lines PA 0-4 will be 10001 = 17, thereby signifying that one sample of pattern PT17 is to be transmitted during that particular time slot.

(e) Of course, during the next time slot TS24, the signals TT 0-5 may have a different value representing a different one of the forty-eight possible tones, and the output PA 0-4 from memory 44 60 will take on a different value to identify that one of the thirty-two sound patterris forming part of the selected tone.

The conductors PA 2-4 lead to a 3:1 gated decoder 46 which has eight output lines connected to enabling chip select terminals CS 0-7 on the respective chips CHP6-CHP, . The simple decoding 9 GB 2 076 614 A 9 truth table is set out as Table I (located at the end of this specification). Briefly stated, since it is known that the individual chips CHP,-CHP7 each contain four sound patterns, then as the pattern signals take on values in successive groups of four (0-3, 4-7, etc) then a successively higher one of the chips (CHPO, CHPI, etc) should be enabled to effect readout of a sample within the desired pattern.

Thus, when the signals PA 0-4 are 10001 = 17, identifying PT1., the signals PA 2-4 are 100 = 4 5 and the decoder 46 applies a "l " level voltage to terminal CS4 to enable chips CHP, (and only C'HP4).

The conductors PAO and PAl normally feed their signals to lines A8 and A9 in the address bus AO-9 so that the appropriate block, of the selected chip, containing the selected pattern is addressed.

The signal PAO passes through an EXCLUSIVE OR gate 48 to reach the line A8, but it will be assumed for the moment that such gate passes the signal unchanged. Table 11 confirms that when the two signals 10 PAO and PAI take on four possible combinations 00, 01, 10, 1 land the address signals A8, A9 in a ten bit address word AO-A9 correspond thereto, then the corresponding one of blocks BLK 0-3 will be the one addressed on the enabled chip with the particular word location within that block being determined by the address signals AO-A7. To pursue the example set out above, if the signals I& PAO-4 have values 10001 = 17, then with PA2-4 having values of 100, chip CHP, will be enabled, and with PAO, PAl having values of 01, block BLK2 on that chip will be selected and the particular sample read out to the bus B will lie between address locations 256-511, i.e., will be one of the samples for pattern PT17. Thus, when a selected sound PT, is identified during any tone time slot TS, by the signals PAO-4, then readout of a sample from the corresponding pattern PT7 stored in the TP ROM will be enabled.

The particular sample readout from within the selected pattern will be determined, however, by the lower order address signals AO-A7. These signals change from cycle-to-cycle in order that the samples of the preselected sound (always read out in the same time slot) will be scanned, and so that the necessary scan sequences are produced. In keeping with an important feature of the present invention a read/write memory is employed to provide the particular sample address signals during each 25 slot of each cycle and to change the particular sample address signals appearing in a given time slot from cycle-to-cycle. As shown for the present embodiment, a 48 x 8 Next Sample RAM 50, when read, produces "next sample address" signals on its eight output lines NSO-7, those signals being taken into a gated input register 51 whose output on lines SA6--SA7 forms the eight lower order bits AO-A7 of an address signal applied to the TP ROM chips. The memory 60 is connected such that it 30 always reads out a word, from the address signalled on the conductors CTO- 5, unless "writing" is enabled by a "l " level existing in a "next sample write" signal NSW (in which case the multi-bit signals at its data input are written into the address location then signalled on conductors CTO-5). The register 1 is one which functions simply to feed its input signals to its output lines except when a control signal CRCK is low, in which case the contents of the register, and its output signals, are frozen at their last- 35 gated values, regardless of how the input signals may change.

Now, as the number signalled at CTO-5 changes from 0 through 47, the forty-eight previously stored words in the next sample RAM 44 are successively read out and transmitted through the gating register 51 to conductors SAO-7. During any tone time slot TS,, those signals form eight bits AO-A7 on the address bus AO-A9 leading to the TP ROM chips and identify the sample address within a block 40 of two hundred fifty-six locations from which a sample is to be read.

To further pursue the example set out above, if during time slot TS23 (when signals at CT 0-5 represent the decimal number -23"), the signals previously formed and stored (in a manner to be described) at address location 23 in RAM 50 are read out to conductors NS 0-7. Assuming that such signals pass directly through register 5 1 to appear at SA 0-7 and A 0-7, and that such signals are 45 11000001 = 93 (and recalling that chip CHP4 has been enabled with A8 and A9 address bits at levels 01), then a sample of pattern PTj,, and specifically the one at address location 449 on CHP4, will be read out to appear on the bus B. This sort of action occurs during each tone time slot of each cycle so that signals representing one sample of a sound pattern preselected for each slot appear at the output bus. As will become apparent 50 below, except in the case of fixed tones, which are optional in the practice of the invention, the preselection is unlimited; a sample of any preselected sound may be transmitted during the successive occurrences of any time slot.

As noted above, however, as each time slot recurs during successive cycles, successively different ones of the samples in the preselected sound pattern are to be read out. It is this changing of the PCM coded values each cycle (e.g. every 125 It sec.) which later enables the sound to be reproduced as audible sound waves. In a way to be described hereinafter, the "next sample address" signals appearing in a given slot of one cycle are replaced (after they have been used) with a new or next value to be employed during the same slot of the ensuing cycle. This is done by deriving the new sample address through the operation of logic circuits 65 (labelled logic A) cooperating with a sequence memory 56, a 60 read/write control RAM 58, an incrementing or decrementing adder 59, a first sample memory 60, and a 2:1 multiplexer 61 (MUX 8) all of which cooperate in the forming and writing of the next sample address into the next sample RAM 50 during any given time slot.

GB 2 076 614 A 10 3. Forming and Storing Next Sample Addresses As explained above, when samples are initially stored in the TP ROM, the address of the first sample (within its block, and representable as eight bits AO-A7) for each of the patterns PT6-PT31 becomes known. Moreover, during any time slot TS, the output of memory 44 on lines PA 0-4 represents numerically the pattern PT, which has been preseiected to have its samples transmitted during recurrences of that time slot. In order to produce and make available signals which represent the -first sample address" of any particular pattern PT,, a readable memory in the form of a First Sample ROM 60 is set up by initially storing therein thirty-two eight bit words representing the address (in TP ROM) of the first samples in the thirty-two respective patterns. The memory 60 is "read" by applying the signals PA 0-4 to its address fines and with the result that during any time slot TS, when the signals PA 0-4 identify the pre-selected tone pattern PT,, for that slot, signals appear at the memory output lines FS 0-7 which represent the first sample address of that pattern PT.. In keeping with the invention, such signals are utilized to effect proper scanning of the samples of the selected pattern, as will be explained below. It should be remembered that the signals at FS 0-7 contain eight bits and thus correspond in orders to the address signals on lines A 0-7.

To carry out one aspect of the invention, means and steps are provided to detect when the signals SA 0-7 (and A 0-7), which in any time slot change from cycie-to-cycle, represent the first sample of the preselected pattern. For this purpose, the signals at FS 0-7 and SA 0- 7 are fed to the logic circuits 55, the latter being described below. The signals FS 0-7 are also fed to the "B" input of a 2:1 multiplexer 61 here labelled NUX 3. The latter applies to the data inputs of the Next Sample RAM 50 20 either the signals PS 0-7 or the eight bit output from the adder 59, depending upon whether a signal applied to its Ena terminal from an OR circuit 64 is respectively high or low. Generally speaking, the logic circuits 55 determine the level of that latter signal by producing a -first sample select- signal FSS. - Also the logic circuits create an---addercontrol" signal AC which, when low or high, causes the adder 59 to produce output signals which numerically are one greater or one less than the value represented by 25 the input signals SA 0-7 applied to its input. Recalling that the signals SA 0-7 represent the address of a sample being read during any time slot of the present cycle, it may be seen that if the adder 59 adds one, its output represents the address of the next sample to be read during the next cycle for an ordinary scan of samples in ascending address order.

4. Controlling Scan Sequences At this point, it will be helpful to explain the nature of the various types of scan sequences which may be required for different sound patterns, depending upon the shape and symmetry of the cyclic analog wave which is to be ultimately reproduced and converted into sound. Generally stated, if a wave has no symmetry within a cycle, samples representing one whole cycle C are included in its pattern, and the samples are repeatedly scanned in first-to-last order. This case is illustrated by the wave 70 in Figure 8A, where the vertical lines represent the magnitude and signs of the samples of a corresponding stored pattern. The pattern would be scanned from the first to the last sample, and the scan sequence Will involve straight repetitions of that scan, as represented by the series of downwardly directed arrows indicating that the TP ROM memory pattern is -scanned down- by numerically ascending address signals. Almost any desired continuous sound may be represented by an integral number of multi-bit 40 samples which are, in effect, taken at 125 It sec. intervals.

Figure 813 illustrates a cyclic analog wave 71 (which happens to be a single frequency sinusoid) having haif-wave, opposite polarity symmetry. In this case only samples for the first half cycle C/2 need be included in the pattern or set of stored samples, thereby reducing the required memory capacity. The wave is signalled digitally by (i) scanning the sample first-to-last, (11) then scanning the samples first-to- 46 last, but complementing the sign of each sample as it is transmitted, and repeating that sequence over and over. This characteristic, i.e., that the signs are to be changed during alternate scans, will here be designated by the letter S, standing for---signchange.---The alternate arrows of solid and dashed lines in Figure 813 symbolically designate that the samples of the patterns during each scan are taken by -reading down- through successive addresses (ascending order of address numbers) to scan first-to- 50 last, the solid arrows indicating that the samples are read out as originally stored and the dashed arrows indicating that before reaching the final output of the tone source, the sign bits of the sample signals are complemented to change the sign.

Figure 8C shows a cyclic analog wave 72 such as might result from the combination of two sine waves. Observe that while a full cycle extends over the period C, the second half cycle C/2 is identical to 55 the first half cycle if the second half cycle is viewed in a -reverse time direction---. This means that a plurality of samples for only the first half cycle C/2 may be stored as a sound pattern, and the entire cycle will be represented digitally if the samples are first scanned in first-to-last order, then scanned in last-to-first order, and that sequence repeated. This characteristic is here designated by the symbol R, standing for -reverse directions- for alternate scans. The alternate arrows pointing down and up 60 pictorially represent that sequence.

Figure 8D shows a wave 74 having both the characteristics S and R explained above. That is, samples for the first half wave C/2 may be stored to form a pattern for the wave; but to reproduce the entire cycle C, those samples are to be scanned initially in first-to- last order with stored sample signs, 11 GB 2 076 614 A 11 and then in last-to-first order with the sign bit of each sample changed before final outputting. The arrows alternately reversed in direction and alternately dotted symbolically represent this scan sequence, and indicate that any wave may have two or more of the characteristics here noted.

The wave 75 shown in Figure 8E is intended to illustrate what is called the---fastsample repeat characteristic. Observe that the half cycle duration is such that the zero magnitude at the end of the 5 first half cycle does not coincide with one of the sampling instants whic are spaced at 125p sec.

intervals. One may "fudge" the cycle period of a wave such that a zero crossing occurs midway between two sampling instants (with the first sample instant always at a zero crossing) to create a sound whose wave is of almost any frequency and shape, and without exceeding industryaccepted frequency tolerances. In such cases, after the samples representing the first half cycle C/2 have been scanned, the 10 last sample LS may be repeated to form, in effect, the first sample output for the next reverse order.scan. The 1ast sample repeat- characteristic may be designated by the letter--- V,and in the symbolic arrow depiction of scan sequences it is shown as an L beneath each downwardly directed arrow. It will be apparent that the wave 75 in Figure 8E results in a pattern of samples which is to be treated with both the L and R characteristics.

With the foregoing in mind, Table X will be understood as showin that any pattern of samples may have any combination of three sequence characteristics L, R and S making eight possible composite scan sequences which are symbolically shown by arrows. Of course, when any sound pattern is initially stored in the TP ROM, its sequence characteristics will be known, and they may be represented in a three-bit binary word (havingeight possible values) as shown in the second, third and fourth columns of 20 Table X.

In keeping with the present invention, the sequence character of each of the patterns PT6-PT,, is represented by a three-bit data word stored at corresponding addresses of a 32 x 3 readable memory 56 which in Figure 2A is labelled -SEQUENCE ROM---. The memory is read, during each time slot, by applying the signals PA 0-4 to its address lines, so that its three output lines carry signals SEQ L, SEQ R, SEQ S at---1---levels when the pattern PT, preselected for that time slot has those respective characteristics. For example, if the pattern P T. were that for wave 71 of Figure 8B, the output signals would be 001; and similarly for Figures 8C, D, E the output signals would respectively be 010, 011 or 110. During each time slot of each cycle, therefore, the logic circuits 55 receive three signals L, R and S which collectively designate the scanning sequence with which the pattern preselected for that time 30 slot must be treated. Such signals will determine the scan sequences which are executed as a large number of cycles occur as noted below with reference to Figure 5.

As treated briefly above, the adder 59 may form a next sample address by incrementing or decrementing the present sample address (signalled at SA 0-7) in the mid portion of any scan (up or down). But a scan down ends when the last sample of the pattern is read out, and the following scan 35 may require (i) next reading out the first sample, (ii) next reading out the next-to-last sample, or (iii) repeating the last sample and followed by the first or the nextto-last sample and in any of those cases either with or without a change in the sign of the sample signals as they are ultimately transmitted to the final output bus OB. Moreover, when the first sample is reached at the end of a "scan up", the following scan must begin always with reading of the second sample. in keeping with the invention, the 40 scan conditions are sensed and the correct one of these possibilities is executed.

As a component useful in accomplishing that objective, a 48 x 3 control RAM 58 is associated with the logic circuits 55. Like the next sample RAM 50, it normally always reads out signals from the address supplied to its address lines via the control signal conductors CT 0-5; but when a "control ram write- signal CRW applied to its write enable terminal W is at the "1" level, then it instead writes the 45 signals WDL, WDR, WDS, then applied to its data inputs, to the address location then signalled at CT 0-5. The data signals WDL, WDR, WDS written are formed by the logic circuits 55, and the output signals RDL, RDR, RDS read from the control RAM 58 are used by the logic circuits 55 as will be described below.

(a) Next Sample Logic Circuits (Figure 5).

Before taking up Figure 5, refrence will again be made to the timing circuits 36 shown in Figure 4 to explain the timing with which data is "written" into the Next Sample RAM 50 and the Control RAM 58 by the signals NSW and CRW, respectively. It will be seen that these signals are derived from a one shot circuit 80 (monostable multivibrator) which is triggered by a voltage rising edge applied to its input terminal Tr, and so that its Q output terminal rises to from an output pulse CRW of predetermined 55 length. The terminal Tr is fed from an AND gate 81 receiving (i) the CLK signal and (ii) the output of an OR circuit 82 which receives the TONS signal and the signal INIT (to be later discussed below). For the moment, it may be seen from Figures 6A and 6B that when signal TONS is high, then the AND gate 81 causes one-short circuit 80 to be triggered on the next rising edge of CLK, so that a relatively narrow output pulse CRW is produced beginning substantially at the mid point of each 2T interval which forms 60 one of the tone time slots. See Figure 6A. The signal NSW is formed by an AND gate 84 fed with CRW and the inversion WDL of the write data L signal WDL produced in the logic circuits 55. In most situations, the signal WDL resides at a 1 level, so signals CRW and NSW are identical as shown in Figure 6A. The point to be observed is that in most time slots, new data is writted into memories 50 and so 12 GB 2 076 614 A 12 58, the former receiving the output of the multiplexer 61 (Figure 213) and the latter receiving the thenexisting outputs WDL, WDR, WDS from the logic circuits of Figure 5 with the data being written into an address location signalled on conductors CT 0-5 and representing the then-current time slot. But such writing occurs only after the first portion of the active time slot (2T wide, as shown in Figure 6A) has 5 expired.

Referring next to Figure 5, the logic circuits include means for detecting when the last sample of any pattern is, during any time slot, being read from the TP ROM. As here shown, the detection is easily made by an AND gate 90 receiving the signals at SA 0-7 (the same as A 0-7) and producing a signal called---255" when they are all 1's. Since, as noted above, the last sample of each pattern is stored in the last location of its block in a TP ROM chip, the signal 255 will appear only when a last sample is 10 being read, i.e., when address lines AO-7 are receiving an eight bit address number which is equal to the decimal value 255.

Further in keeping with the invention, there is a detection and signalling of the fact when the first sample of any pattern is, during any time slot, being read from the TP ROM. As here shown, an eight bit comparator 91 receives during each time slot the signals SA 0-7 and the output FS 0-7 read from the first sample ROM 60. Its comparison output signal CMP goes high only when the two inputs are identical and will thus be high at the beginning of any time slot when the first sample of any pattern is being read out of TP ROM because the first sample ROM 60 is ared, during any time slot, by address inputs PA 0-4 (Figure 2A) which identify the pattern preselected for that time slot.

As also shown in Figure 5, the output signals RDL, RDR, RDS read from control RAM 48 form inputs to the logic circuits and are "saved" temporarily in a latch register 92. The latch output signals are designated LOL, LOR, LOS the terminal letters L, R, S carrying the significance explained above. The signals RDL, RDR, RDS are clocked into, and become the output signals LOL, LOR, LOS of, the register 92 once during each time slot by the rising edge of signal CRCK. From Figure 6A, it will be seen that entry of signals into the register 92 occurs roughly 1/2 T after each time slot of 2T width begins.

The output signals SEQ L, SEQ R, SEQ S from the sequence ROM 56 also form inputs to the logic circuits of Figure 5 and are designated simply L, R, S. As each time slot occurs, the signals PA 0-4 identify the sound pattern preselected for that slot, and the signals L, R, S collectively represent the scan sequence characteristics for that pattern.

There are, of course, two scan directions, up and down, meansing that the TP ROM addresses fora 30 given pattern are to be taken in numerically ascending or descending order during a given time slot of successive cycles. In such cases, the apparatus of Figure 5 makes the adder control signal AC a 0 or 1 during the progress of a single scan so that when address for sample Sj appears during a given slot of a given cycle Ci, the adder output becomes the address for sample S,+, or sample S,-, to be used during the next cycle C,+1. That is, the adder/subtractor 59 adds one subtracts one to its input signals SAO-7 35 and signals the result at the -A- input of multiplexer 61 (Figure 213). To control the adder 59, the signals 255, R, LOR and CMP are applied to logic gates 94, 95, 96 (Figure 5) which determine the 1 or 0 level of the signal AC according to te'truth table set out in Table Ill. It may be observed that if the R characteristic is absent (and signal LOR remains always 0), then signal AC is always low and successive address from the adder are incremented. If the R characteristic is present, however, then when the fast 40 sample in a -downward- scan is reached (and the signal 255 =---1 "), the signal AC becomes a---1 -, and an upward scan begins. It will continue high (with LOR = '1 -) until the first sample is reached and the signal CIVIP becomes a---1---(after which LOR reverts to "0") whereupon a downward scan will begin.

The signal FSS for controlling multiplexer 61 is formed by a single gate 98 which is, in effect, an AND gate receiving 255 and R inputs. The signal FSS will, as shown in the truth table of Table IV, always be -0- except when the last sample is being read (255 =---11 -) and the characteristic R is absent. In the latter case, the signal FSS becomes a---I-, and the multiplexer 61 is conditioned to send the signals at FS 0-7 (instead of the adder outputs) to the data inputs of the Next Sample RAM 50 for writing when signal NSW appears.

The signals WDL, WDR, WDS are formed in the apparatus of Figure 5 according to conditions in a given time slot of one cycle so asito be usable in the -same time slot of the next cycle. They control what the next sample address will be, at the start of a new scan, when the end of a given scan is reached; and they are preserved (repeatedly written into and read from the control RAM 58) as each sample is used during a scan.

Consider first the signal WDL. It is formed by a logic gate 99 from the signals 255, LOR, L. As 55 shown by Table V, signal WDL becomes a---1---during the terminal portion of any time slot, if, and only if, (i) the fast sample is then being read (so signal 255 =---1 "), (H) the signal L is '1---(indicating the preselected pattern has the -last sample repeatcharacteristic), and (iii) the signal LOL is -0 (indicating that the sample used for the same time slot of the preceding cycle was not the last sample).

When WDL does become "1", it signifies that the last sample should be repeated and used again in the 60 same time slot of the ensuing cycle, and thus that the same sample address as that presently signalled at SA 0- 7 should be used during that time slot of the ensuing cycle. When WDL is a '1 ", WDL in Figure 4 becomes a "0", and the signal NSW does not appear, so the sample address data in RAM 50 (at the address signalled on CT 0- 5) is not changed. It is to be noted that WDL goes to a 1 level during 45, 13 GB 2 076 614 A 13 only one cycle when the last sample is reached at the end of a downward scan, because when WDL occurs in a given cycle it is written into the control RAM 58, so that the signal LOL becomes---1---during the next cycle to inhibit re-creation of the signal WDL.

Figure 5 shows that, during a given time slot of a given cycle, the signal WDR is formed by logic gates 100, 101, 102. The truth table for their operation appears in Table VI. It will be seen that WDR becomes a--1---only if the pattern being scanned has a -reverse directionscharacteristic and the signal R is a---1 -. When the last sample of the pattern is reached in a downward scan or when LOR is a 1, the output of OR circuit 100 is a 1. Only under these conditions can WDR become a 1. But further, if it-is the LOR signal which produces a 1 from OR circuit 100, then WDR can be a '1 " only if (i) 255 = M- and R =---1 " to make the output of gate 101 have a 1 level and (ii) if CMP = 0. Thus, for any pattern having a "reverse direction-, characteristic, WDR becomes a---1 " when the last sample in a downward scan is reached, remains a 1 during the ensuing upward scan (because WDR is written during each cycle and read to make LOR a 1 during the next cycle), but reverts to a 0 when the first sample is reached at the end of an upward scan (because CMP then- becomes a 1).

The signal WDS is created during alternate scans of a pattern having the alternately change is signs- characteristic S. It is formed by gates 104 through 108. Tables VII and Vill contain the simple truth tables for gates 104 and 105 to indicate how signals SIG 1 and SIG2 relate to 255, L, CMP and R. Table]X reflects the truth table for WDS as formed by gates 106, 107, 108. One sees immediately that WDS can never be---1---if the S characteristic of the pattern being treated is absent and the signal S is "0". On the other hand, the signal WDS becomes a 1 if signal S is a---1 " and the sample being treated is 20 the last sample in a downward scan when LOS is 0, after which WDS and LOS remain at a 1 level in the same time slot of succeeding cycles during the ensuing scan until either the first or last sample is reached in an upward or downward scan.

In a given time slot of a given cycle, the outputs RDL, RDR, RDS from RAM 58 are first latched into the register. They are the same as the signals WDL, WDR, WDS formed during the previous cycle and 25 written into the RAM 58, and in a given cycle they become the new latch register outputs LOL, LOR, LOL. This creates, during the given cycle, the signals AC and FSS at the proper levels, and also forms new (although perhaps unchanged) values of the signals WDL, WDR, WDS which are then written (at an instant approximately mid-way through the time slot) into the RAM 58 without, at that instant, changing the signals LOL, LOR, LOS.

During each time slot when the signal LOS is at a---1 " level, and it will so remain during a given time slot of all the cycles required for one complete scan of the samples for the preselected pattern it is used to complementally change the sign bit of the eight-bit sample signals read from the TP ROM. As shown in Figure 2B, the output signal LOS from Figure 5 is applied to one input of an EXCLUSIVE OR circuit 110 which receives the eighth bit (sign bit) signal from the TP ROM output bus B. If LOS is a 1, the stored sign bit is inverted before being applied to a final eight bit gate 112 whose output leads to the final output bus OB. Thus, the outputs from the TP ROM are applied, when the gate 112 is enabled, to the final bus OB with the sign bit selectively non-inverted or inverted as determined by the signal LOS.

A moment's comparison of Table X with the operation of Figure 5 will confirm the following: 40 (a) Once a scan is started (down or up) the signal AC remains the same (0 or 1) during a given time slot of recurring cycles. The output of the adder 59 thus represents an address number which is one greater or one less than the---thiscycle" address signals at SA 0-7 and this is written into the next sample RAM to be used during the next cycle.

(b) It is only during scan sequences of a pattern having the R characteristic that samples are 45 scanned in an---upward"(numerically descending address order) direction. But an upward scan begins only after each downward scan ends (the last sample is read and 255 =---1 "), and it ends when the first sample is reached so that the signal CMP becomes---1 -.

(c) The last sample is repeated at the end of each downward scan of a pattern having the L characteristic.

(d) Absent the R characteristic for a pattern, when the last sample is read, or the last sample is repeated if there is an L characteristic, then after each downward scan is completed (as detected when signal 255 becomes a---1 "), a new downward scan is begun by jumping back to the first sample address. This is accomplished when the signal FSS signal becomes a---1 " so that multiplexer 61 is conditioned to write the output of the First Sample ROM 60 (rather than the output of the adder 59) into 55 the next sample RAM 50.

(e) When a pattern has the S characteristic and the signal S is a 1, then on alternate scans the signal LOS is a 1 and the EXCLUSIVE OR circuit 110 inverts the sign bits read from the TP ROM. The end of a scan (after which the signal LOS changes) is detected when signal 255 becomes a 1 (in the case of a downward scan) or when the signal CMP becomes a 1 (in the case of an upward scan).

(f) The signal WDL appears as a 1 and recirculates through control RAM 58 for one cycle to cause the last sample to be repeated, by the AND circuit 84 of Figure 4 inhibiting the writing of a changed sample address into the next sample RAM 50 at the end of each "downward" scan of a sample having the L characteristic.

(g) The signal WDR is created and recirculated through the control RAM 58 to form the signal LOR 65 14 GB 2 076 614 A 14 during "upward" scans of a pattern having the R characteristic. This causes the signal FSS to be -1 and makes the adder 59 form next sample addresses by decrementing.

(h) The signal WDS is recirculated through the control RAM 58 to form the signal LOS during alternate scans of a pattern having the S characteristic.

All of the foregoing is accomplished with respect to scanning of a particular pattern which has been preselected for a given time slot, the one scan occupying as many cycles as there are samples in the pattern. When one scan ends, the next begins on the succeeding cycle so that the proper samples are outputted at 125,u see. intervals in a given time slot on a continually repeating basis. Subseq - uent demultiplexing, decoding and filtering of the samples will therefore produce a counterpart analog wave transducable by an earphone or loud speaker into a counterpart sound.

The different types of scan sequences are illustrated by Table XI which shows how the samples are read out in succession to produce scan sequences for the eight sequenced characteristics set out in Table X. Each block within a column represents conditions during the same time slot of one cycle. The first line within a block indicates the active latch output signals LOL, LOR, LOS as a three-bit word. The second line within each block represents the address (within a TP ROM block and as signalled on lines 15 SA 0-7) of the sample being read during that particular cycle, recalling that the last sample is at address 255 and the first sample of the pattern is at some known first sample address FSA. The remaining lines within any block illustrate the values of certain other designated signals.

By way of example, the second column of Table XI depicts the scan sequence for a pattern which has the characteristics LRS = 010, designating that the samples are to be scanned alternatively up and 20 down. In the first and second blocks of Column //2, addresses 253 and 254 are shown as being read in succession during a downward scan. In the third block, address 255 (last sample) is being read out, so the control signal AC reverts from 0 to 1, the WDR = 1 is formed so as to be written into the control RAM 58. In the next cycle (fourth block), therefore, the adder 59 has formed the next address 254 by decrementing and the value 254 is being read from RAM 50 so an upward scan begins with reading of a 25 sample from address 254. The signals AC and WDR remain high in the following cycles as the upward scan proceeds until the address being read is reduced to that of the first sample address FSA. At that point, the signal CMP becomes high, so that AC and WDR revert to 0 and a downward scan begins.

From the foregoing example, the remainder of Table X1 will be fully understandable to one skilled in the art as illustrating the basic steps by which the apparatus of Figures 2A and 2B (and as detailed in 30 Figures 4 and 5) scans a pattern preselected for any time slot and produces the required scan sequences which are designated by a three bit characteristic word stored in ROM 56 for each of the patterns. Each individual scan, which involves using all of the samples of a pattern, is carried out in one of fourfashions, as indicated by Table X. The first fashion scan takes a pass through all samples from first-to-last with true signs; the second fashion scan is the same but involves complementing the sign 35 bits of the samples; the third fashion scan takes all samples last-to- first with true signs; and the fourth fashion is like the third but with complemented signs. The last sample repeat is a special case. But the sequence of scanning produces the proper scan fashions in the correct order according to the characteristics of the stored sound pattern.

5. Operations and Relative Timing Within One Time Slot As mentioned above with reference to Figures 6A and 6B, the counter 35 (Figure 2A) counts from 0 to 47 during each cycle to measure off forty- eight tone time slots, there being forty-eight voice channels or slots in the same cycle. Although the counter resides in each of the even count states (0, 2, 4,6.... 46) for intervals of 6T, it is only the last 2T of such intervals which form a tone time slot of 1.3 u see., as labelled above the CRCK waveform in Figures 6A and 6B. Observe from count state 1 in Figure 6A that odd count states begin with the signal CRCK low for something less than half of the corresponding 2T interval, and that signal is high during something more than the last half of the time slot duration. This same relationship exists for signal CRCK during the time slot signalled by an even count state, except that CRCK has been driven low at the end of the preceding odd count state and it 5Q switches high only after a portion of the 2T interval for an even numbered time slot has elapsed.

Figures 7A and 7B graphically indicate how signals change during even and odd count state time slots, it being assumed for example that they are time slots TS22 and TS23 out of the series TSd-TS47 within a given cycle Ci. The timing signals CLK, CLK and CRCK are shown on a time scale expanded in relation to that of Figure 6A, each of the slots TS22 and TS23 being 2T in duration. Figure 7A makes it more evident that a propagation delay P.D. may exist between the instant when CLK swings high and 55 the instant t2 when CRCKswings high.

Wave form 120 in Figure 7A represents the gate control signal GC created in the timing circuits 36.

As seen from Figure 4, this latter signal is formed at the G output of a D-type flip-flop 121 which is preset to the 1 state so long as the signal TONS is high, but which is clocked to the reset state by the rising edge of the signal CLK appearing when TONS is low. Thus, as shown in both Figures 6A and 7A, 60 the signal GC is normally low; when signal TONS goes high at instant tV GC swings high after the first portion of the 2T interval has elapsed in an even number time slot TS2, and it falls for a brief time but rises again at instant t 2 in an odd numbered time slot TS23. In essence, the gate control signal GC is high over the scan of both even and odd time slots, its being low in the early portion of a time slot having no GB 2 076 614 A is adverse consequences. Yet the signal GC is low during all or at least the latter portions of voice channels, as shown in Figure 6A.

The gate control signal GC passes through an AND gate 122 (Figure 2A), assuming the signal SCHED is high, to become the final gate enabling signal ENFG applied to the control terminal EN of gate 112 (Figure 213). Thus, during each tone time slot when one sample is being read from the TP ROM, the output of TP ROM is passed from bus B to final output bus OB assuming there is no overriding effect of on-off scheduling as hereinafter described, and recalling that the sign bit of a sample may or may not be inverted by the EXCLUSIVE OR gate 110 as noted above. During some interval during the last half of each tone time slot, the first order multiplexer 22 (Figure 1) picks the sample signals off of the bus OB, as is well known in the art.

Wave form 124 in Figure 7A shows again the signals CRW and NSW which are illustrated in Figures 6A, B and produced by the flip-flop 80 in Figure 4. Noteworthy is the fact that these signals exist for a short time beginning at an instant t3 within each time slot, so that if data is newly written ilito RAMS 50 and 58, such writing occurs roughly midway through each time slot.

The output of the counter 35 is represented as shaded areas which change at the beginning instant t, of each off tone time slot, and which exist to numerically represent the time slot at the beginning instant of each even numbered time slot. In Figure 7A, the two shaded areas of the bar 126 show the count state or control signals CT (appearing on conductors CT 0-5 in Figure 2) as equal to 22 and 23 during time slots TS22 and TS23, respectively.

The shaded bars at 128-133 in Figure 7A represent various signals which change from tone Slot 20 to tone slot but which remain fixed during one given slot because they are under control of the count state signals CT. Specifically the commanded tone signals TC at the output of a Tone Select RAM (Figure 2A) are read (as hereinafter described for switched tones) from an address signalled by the control signals CT from the counter 35 and passed through the first multiplexer MUX 1. Thus, as the count states change, and different time slots occur, the signals TC change. As a concrete example to use 25 in considering Figures 7A and 713, it is assumed that there has been stored at address locations 22 and 23 command signals numerically representing tones TN3. and TN,,, respectively, as the preselected tones for time slots TS22 and TS2.. Thus, the bar 128 indicates in Figure 7A that the output signals TC read from RAM 135 during time slot TS22 are equal to 36; and in time slot TS23 are equal to 18.

For switched tones (in time slots above TS,, as explained below) a second multiplexer MUX 2 30 (Figure 2A) is enabled to transmit its A input signals to its output, where they become the signals at TT 0-5 and identify the preselected one of the tones TNC-TN47. Thus, in keeping with the example given above, the shaded bar 129 in Figure 6A indicates that the output of MUX 2 constituting tone identifica tion signals TI, is also numerically equal to 36 and 18, respectively, during slots TS22 and TS23, The tone ID signals T1 identify the partfeular tone which is preselected fora particular time slot. 35 The shaded bar 130 confirms that as the signals (T1 (atTTO-5) change from slot-to-slot, the output signals from the Pattern Select ROM 44 also (but need not necessarily) change. Let it be assumed for purposes of discussion that tone TN3. is to be formed by sound pattern PT13 (out of the plurality of PTO---PT3,) and schedule SCH,, (out of the plurality of SCH,- -SCH,,). Further, assume that tone TN,, is formed of sound pattern PT27 and schedule SCH6. Figure 7A in illustrating this example thus 40 confirms that the numerical values of "ll 3---and---27---would have been initially stored at addresses 36 and 18 of the pattern select ROM; and the numerical values of "110---and 'W' would have been stored at addresses 36 and 18 of the schedule select ROM 45. Thus, during time slots TS22 and TS23, the output PI (on lines PA 0- 4) from the pattern select ROM 44 will represent "ll 3" and "27" to identify patterns PT,3 and PT27 as the respective preselected sound patterns for those slots.

The shaded bar 131 in Figure 7A correspondingly indicates that the output signals SS from Schedule Select ROM 45 will numerically represent---10--and 'W' during time slots TSU and TS,., identifying SCH1. and SCH6 as the respective preselected schedules.

Since the pattern identification signals P I applied to the address lines of the first sample ROM 60 change from slot-to-slot to represent the preselected sound pattern for each slot, the shaded bar 132 50 indicates that the output of that ROM has different values during time slots TS22 and TS23. It is assumed, to pursue the foregoing example, that patterns PT13 and PT17 have their first samples located at block addresses of 156 and 231 respectively, these numbers have been initially stored at addresses 13 and 27 of the first sample ROM. Thus, Figure 7A indicates that during time slots TS22 and TS23 the output of the ROM 60 at FS 0-7 respectively represents the numerical values of '156- --and '231 ". 55 The sequence ROM 56 is read by the signals P I applied to its address lines PA 0-4 during each time slot, such signals representing the preselected pattern. Since the latter signalschange from slot-to slot, the output SEO. L, SEG R, SEQ S from the ROM 56 represents the scan sequence characteristic of the preselected pattern and changes from slot-to-slot as illustrated by the shaded bar 133. It is here further assumed that pattern PT13 has the characteristics of Figure 8A and sequence No. 1 in Table X,60 whereas pattern PT.7 has the characteristics of Figure 8C and sequence No. 2 in Table X. Thus, the output of the sequence ROM is shown in Figure 7A as being 000 during time slot TS22 and as being 010 during slot TS23.

The shaded bar 134 in Figure 7A illustrates the output of the decoder 46 (Figure 213). Since the decoder is enabled by signal CRCK, it is turned off between instants t, and t2 of each time slot, but 65 16 GB 2 076 614 A 16 otherwise enabled. Thus, no reading of the TP ROM occurs until some portion of a time slot has elapsed. Carrying forward the example assumed above, with the preselected patterns for TS22 and TS23 being PT,3 and PT2, it will be seen from Table 1 that the decoder outputs become "3" and -6-, respectively, and thus chips CHP3 and CHP, (Figure 213) will be respectively enabled during slots TS22 and TS23 SO 5 that one sample of PT13 and one of PT2, may be read out.

The shaded bars 135 and 136 in Figure 7A represent the outputs of the Next Sample and Control RAM's 50 and 58, respectively. As the signals CT on lines CT 0-5 changes from slot-to-slot, they cause reading of successively higher address locations in these RAM's, so that between instants t, and t3 of each time slot, data previously written at those locations is read. Thus, the---nextsample" output at NS 0-7 during slots TS22 is here shown, as an example, as being "212" read from address location 10 ---22" (and having been written there during the slot TS22 of the previous cycle C,-,). Likewise, outputs RDL, RDR, RIDS of Control RAM 58 is here shown as having the value 000 read from address location ---22" of RAM 58 (and having been written during the previous cycle). But at instant t, (and before any change in the next sample and control RAM outputs) the signal CRCK swings from high to low and thus holds or freezes the existing signals at NS 0-7 in the register 51 (Figure 213) so that the signals at 15 SA 0-7 cannot change for the remainder of the time slot This is illustrated by the shaded bar 137 which confirms that the signals SA at SA 0-7 are the same (representing '212--- )as those at NS 0-7 between instants t, and t3 but they do not change at instant t3 when new data is written into the next sample RAM 50 by the appearance of a NSW pulse.

Between instants t, and t2, the logic circuits 55 of Figure 5 generate outputs AC, FSS, LOS, WDL, 20 WDR, WDS based upon the signals LOL, LOR, LOS (latched into the register 92 during the previous time slot TS,1). Such signals are meaningless during that interval, but without adverse consequences. At instant t2 when the rising edge of signal CRCK appears, the outputs RDL, RDR, RDS of RAM 58 is clocked into and frozen in the register 92, forming new signals LOL, LOR, LOS here labelled 000 in the shaded bar 138 of Figure 7B. Thus, from instant t2 of any time slot until it ends, the outputs AC, FSS, 25 LOS, WDL, WDR, WDS of the logic circuits 55 are formed and usable, as indicated by lines 139 and 140 in Figure 7B. The hatched portions of these lines designate that signals AC and FSS have meaningless values between instants ti and t2.

Bearing in mind that readout of a sample (whose address is represented at AO-A9) from the TP ROM to the final bus OB can only occur when the final gate 112 (Figure 213) is enabled and one of the 30 chips CP1-1d---CP1-17 is enabled, and noting the timing for the signal GO (wave form 120) and the decoder output (represented at 134), the sample signals during each of the time slots TS22 and TS2. will exist on the bus OB from the instant t2 until the time slot ends ab represented in Figure 713 by the shaded bars at 141. But this will occur only during the "on" intervals of on/off schedules, as determined by the signal SCHED (Figure 2A) in the manner explained fully below.

Figures 7A and 713 make it clear that after the signals at SA 0-7 are frozen in the register 51 (see bars 138) at instant t2, and the signals RDL, RDR, RIDS are clocked into and frozen as LOL, LOR, LOS in the register 92 (Figure 5), then new and proper values for the signals AC, FSS, LOS, WDR, WDL, WDS are formed by the logic gates of Figure 5 and are fixed for the remainder of the time slot. These signals determine whether the adder 59 produces its output by adding or subtracting one to or from the numerical value of the "this cycle- address signaled at SA 0-7, and whether the data input lines for RAM 50 receive via MUX 3 the adder output signals (if FSS = 0) or the -first sample address" signals at FS 0-7 (if FSS = 1). If the signal LOS is 0 or 1, the EXCL. Or gate 110 causes the sign bit of the sample word read from TP ROM to be true or inverted, relative to its value as originally stored, when it reaches, the final bus OB. The signals WDL, WDR, WDS are formed and ready for writing into RAM 58 so that they have the proper values to be used as the signals RDL, RDR, RIDS during the same time slot of the ensuing cycle C,,, Then at instant t3, the write-enable signals CRW and NSW go high for a short interval, so that the 11 next sample address" then signalled at the output of MUX 3 is written into the time slot address (signalled at CT 0-5) of the RAM 50, replacing the previous contents. Similarly, the signals WDL, WDR, WDS are written into the control RAM 58 at the address signalled on CT 0-5, replacing the previous contents. After the "write enable- pulses CRW and NSW end, therefore, the newly written contents at those address locations are read out and form new values at NS 0-7 and RDL, RDR, RIDS during the remainder of the time slot. This is illustrated at 135 and 136 in Figure 7A where such signals are shown at numerically representing "213" and a three-bit word 000, respectively, during the 55 terminal portion of slot TS22. Such signals are not used during cycle Ci; on the contrary, they have been stored by writing so they can be read again and used during slot TS22 of the next cycle C,, This is the significance of the legends NS,+1,22 213 and RIDi+1,22 000 in Figure 7A, it being apparent that the next sample address will be formed by the addition 212 +1 = 213 in the adder 59, and the RD signals will be 000, fora pattern having the characteristics shown in the first line of Table X and the scanning 60 sequence shown in the first column of Table Xl.

In the case of time slot TS23, however, it has been assumed that the preselected pattern PT27 (for tone TNJ has the characteristics of the second line in Table X, and that the scan in progress is an 11 upward" scan as represented by fourth through the seventh blocks shown in the second column of Table Xl. Thus, in Figure 7A, after instant t3 of slot TS23 the output of RAM 50 at NS 0-7 is indicated as65 17 GB 2 076 614 A 17 NSi+1123 250 because the adder 59 has subtracted (251 - 1 = 250); and the signals RDi+1123= 010 are indicated because WDR and RDR will take on a value of '1 " during successive time slots of an 11 upward- scan.

It will be understood, therefore, that when cycle C,+, is executed and the RAM's 50 and 58 are read by control signals CT = 22 and CT = 23 during slots TS22 and TS2Y the outputs from RAM 50 will 5 be---213---and---250-, respectively, whereas the outputs from RAM 58 will be 000 and 010, respectively.

Of course, and for the reasons explained above, when the last sample is reached at the end of a downward scan, or the first sample is reached at the end of an upward scan, then the signals WDL, WDR, WDL change from the values they had during the previous cycle, and the next scan is properly 10 initiated.

In the case of a sample having the L characteristic, the signal WDL becomes high during the cycle when the last sample is read out at the end of a downward scan. As shown in Figure 4, the AND gate 84 is disabled by the WDL signal in these circumstances, so the signal NSW is prevented from rising to a 1---level. This prevents writing of new data into the next sample RAM 50 during that cycle, so that 15 during the same time slot of the ensuing cycle the last sample will be - repeated- or read-out again. But when that occurs, signal WDL takes on a "0" value, and so during the following cycle a new scan (either up from the last sample or down starting the first sample) begins.

In review, the method carried out by the apparatus here shown and described includes initially storing in the TP ROM at least one plurality of samples S6---S,, constituting a pattern for a cyclic wave; 20 providing preformed address signals (at NS 0-7 and SA 0-7) in a next sample memory 50, during a given cycle C, and a given time slot thereof reading the preformed address signals from that memory to cause readout of a certain sample S, from the TP ROM onto an output bus OB; using the preformed address signals to derive a next set of address signals corresponding to a sample S, I; storing the derived signals into the next sample memory in place of the original preformed signals, to constitute new preformed signals; and repeating that sequence so that in the succeeding cycle C,+,, the new address signals cause the next sample S,+, to be fed onto the bus. That procedure is performed for each of a plurality of time slots with one of the several patterns PTd--PT, preselected for each slot, so that scanning of all samples within a plurality of patterns occurs as the cycles repeatedly recur. But further, the desired scan sequences for any pattern are obtained by initially storing its scan sequence characteristic as a multi-bit word in the sequence ROM 56, and using the read-out word in the derivation of the - next address- signals.

6. Combining Sound Patterns with Schedules To Form Various Tones As noted above, the present invention permits any of a plurality of sounds SD6--SDl represented as sample patterns PT6--PT., to be transmitted in a desired one of time slots TS6--TS47 with any one of 35 a plurality of on/off schedules SCHC- SCH,,, to form any of a plurality of tones TN,7--TN47.Of course, one skilled in the art may routinely choose to follow the teachings of the present invention by adopting a greater or lesser number instead of thirty-two sound patterns, sixteen schedules, forty-eight tones and forty- eight time slots, and it has already been explained that the same sound may be preselected to appear in a plurality of the time slots. Indeed, it is possible to designate several of the forty-eight tones 40 as being formed by the same sound and schedule.

In the preferred embodiment here illustrated the forty-eight tones (whether or not some are identical) TNO---TN47 are established by "pairing" of one sound pattern with one schedule at the time the pattern select ROM 44 and the schedule select ROM 45 are "burned" or loaded with stored data.

Each sum ROM has forty-eight address locations accessible by tone ID signals T16--T'4, numerically 45 signalled as one of the values 0-47 on lines TT 0-5. For example, one may choose tone TN. to be formed by pattern PT, and schedule SCH.9; -tone TN, to be formed by PT, and SCH,,; tone TN2 to be formed by PT23 and SCH4; and so on. It is only necessary that the identification (ID) numbers for the desired pattern and the desired schedule for a given tone be paired by storing them at identical address locations in the ROM's 44 and 45, respectively, so that they will be read when the tone ID signals 50 identify the given tone. To carry forward the arbitrary examples given above, that data initially stored in ROM's 44 and 45 would be arranged as follows:

18 GB 2 076 614 A 18 TONEID ADDRESSLOCAT. DATASTORED TONE SIGNALS IN ROWS 44 & 45 ROM 44 ROM 45 TN,, 0 0 3 9 TN, 1 1 8 15 TN2 2 2 23 4 1 9 a TNX: X X a 1 1 PTy SCHZ The sixteen possible on/off schedules may be arbitrarily chosen but will usually include those adopted as standard in the telephone industry. The "continuous on" schedule will be used in many tones; and the "continuous off" schedule will be provided as an easy way of creating no sound, i.e., a quiet tone. But the other schedules might be, for example, on/off intervals (in seconds) of 0.5/0.5, 1/.5, 1/1-95405, 2/4, and so on. In the practice of the present invention the choice is limitless.

To set up the chosen schedules, another memory chip, preferably a ROM 200 (Figure 2A), is initially constructed or loaded with data viewable as a predetermined number of words (here 120) each containing a pre-chosen number of bits (here 16) such that as the words are read out cyclically in address sequence they are produced the pre-chosen number of parallel bit streams, each stream corresponding to one of the schedules SCH6--SCH,,. The readout period for each address location is chosen as some convenient fraction of a second, e.g., the successive address locations are cyclically scanned at a rate of 1/20 of a second (50 m.s.). By stored sequences of predetermined groups of successive I's and o's in the same bit place of successive stored words, the recurring high/low or on/off intervals in each bit stream may be given the desired time durations.

To make this clear by way of example, it may first be observed in Figure 2A that the signal RST (having a frequency of 8 KHz. and a period of 125,u sec.) is fed through a "divide by 400" frequency divider 201 to create a squarewave (having a frequency of 20 Hz. and a period of 50 m.s.) applied continuously to the input of a rollover counter 202 having eight binary stages interconnnected with gating (as is known in the art) to have a count capacity of 120 (count states 0-119). The counter 202 20 thus occupies each count state for 50 m.s. and counts through one cycle in six seconds. Its eight binary stage outputs are connected to the address lines of the 120 x 16 ROM 200 so that each of the words there is read for an interval of 50 m.s. and all words are cyclically read out every six seconds.

Table X11 shows, partially and as an arbitrary example, the stored contents of the on/off ROM 200 to indicate how different schedules maybe established. Bit bo in all of the words at locations 0-119 is stored as all O's so that bit bo corresponds to the schedule SCHO to establish a "quiet tone" (continuously off). Bit b2 is stored as a string of I's from addresses 0 to 19, a string of O's from addresses 20 to 39, I's from addresses 40 to 59, O's from addresses 60 to 79 and so on. Since there are alternate groups of twenty I's and twenty O's, the bit IJ2 output line of the ROM 200 (corresponding to schedule SCH2) will be high and low for alternate on/off periods of one second during the six seconds 30 of the repeating count cycles of the counter 202. Thus, schedule SCH2 is here shown chosen as an on/off duty cycle of 1/1 seconds.

In like fashion Table XII reveals the following examples:

lq 19 GB 2 076 614 A 19 CORRES. ON/OFF SCHEDULE BIT BIT PATTERN INTERVALS SCH, b,, All O's Continuous off SCH, bl All l's Continuous on SCH2 b2 Twenty l's 1/1 See.

Twenty O's SCH, b, Forty l's 2/4 Sec.

Eighty O's SCH4 b4 Forty O's 2/2 See.

Forty l's SCH, b, Twenty l's 1/5 Sec.

One Hundred O's SCH, b15 Ten l's 5/.5 Sec.

Ten O's 1 1 Thus, it will be seen that any recurring on/off schedule may be given to the signal appearing on an output line of the ROM 200, the on/off intervals being plq where p = nAT and Q = mAT; AT being the period (here 50 m.s.) during which each address is read and n and m being the numbers of l's and O's stored in successive alternate groups. If K is the number of words or address locations in the ROM 200, the counter 202 is constructed to "roliover" through K count states, and a fully count cycle takes K.AT seconds. During each cycle there will be a "on" intervals and b off intervals, where a(nAT) + b(mAT) KAT. The values of a, b, n, m chosen for any schedule are entirely flexible and picked to create the desired schedule. If a schedule SCH, is desired with an on/off duty cycle of 1.5/. 5 in the present embodiment then bit b of ROM 200 would be stored as a repetitive pattern of thirty l's and followed by 10 ten O'sandin such case K=15;AT= 50 m.s.;a=b=3; n=30and m= 10.

Since the counter 202 causes continuous cyclical reading of the addresses in the ROM 200, there are always present at the sixteen output lines of that ROM sixteen signals which have the various chosen on/off ratios for schedules SCH6--SCH,., The four output lines from the schedule select ROM carry schedule identification signals SS numerically representing, during each time slot, the preselected 15 schedule SCH. of the preselected tone TN, then signalled by tone identification signals T1 at TT 0-5. Those signals SS are applied to a known type of 16-to-1 selector 204 having its inputs connected to the sixteen output lines of the on/off ROM 200. Thus, when the signals SS have a value of -9-, the signal on the output line for bit b, will be passed through the selector 204 to a single conductor 204a, making the signal SCHED have alternate high/low or on/off timing corresponding to schedule SCH The signal 20 SCHED, therefore, during every time slot of every cycle is high or low depending upon the on/off intervals measured off in actual time according to the schedule SCH. identified by the signals at SS and forming a part of the tone preselected for that particular time slot.

The signal SCHED controls the AND gate 122 which forms the signal ENFG controlling the final gate 112. Thus, the final gate 112 is enabled during each time slot when the gate control signal GC is high, but this occurs only during the "on" periods when signal SCHED is high. Therefore, sound samples actually reach the output bus OB during the "on" intervals of the preselected schedule and when the sound samples ultimately are converted into sound (after being routed through the switching network and decoded into analog form), a listener will hear the corresponding sound but with the chosen on/off schedule timing.

7. Switching Or Preselecting Tones in Response To Commands In the concrete embodiment here shown, there are sixteen "fixed tones" which are always transmitted in respective preassigned time slots, and the remaining thirty-two time slots may each have any one of the forty-eight available tones "switched into" or preselected for transmission in it. Of course, the invention may be in practice in some of its broader aspects by having all time slots carry fixed tones, or all times slots carry switched or switchable tones. In the present instance, however, time slots TS,-TS,, carry fixed tones and time slots TS,,7-TS,, carry respective tones which are preselected by command signals received asynchronously via the command bus C13 from the central control unit 12 (Figure 1).

As shown in Figure 2A, the counter 35 supplies its output signals as successive control signals 40 CT6--CT,, to the B input of multiplexer 42 (MUX 1), those signals being transmitted as control signals GB 2 076 614 A 20 CT on lines CT 0-5 at all times except when the reset signal RST is high at the beginning of a cycle. The control signals CT exist as respective values CTC-CT47 during, and uniquely identify, each of the tone time slots TSO-TS47 When the numerical output of the counter 35 is below sixteen (during count states 0-15 and time slots TSd-TS,), the output of an OR circuit 220 is low, and such low signal as the EnB control terminal of a second multiplexer MUX 2 causes the tone ID signals TI atTT 0-5 to be the same as the signals CT. Therefore, during time slots TS6-TS, of every cycle, the preselected tone identification signals TI on lines TT 0-5 take on values of 0-15 respectively and call from the transmission of tones TNd.---TN,,during those corresponding time slots. Thus, the first sixteen address locations of the pattern select ROM 44 and the schedule select ROM 45 contain pattern ID and schedule iD numbers paired for the desired sixteen fixed tones TNO-TN,. In the switching network 10 10 of Figure 1 a -connection- may be made to one of the channels corresponding to a given one of the tone time slots TS6-TS1., and the corresponding fixed tone will be sent via that connection because the fixed tone pre-assigned to that channel is always present.

To enable "switching" of tones into the remaining time slots, the desired tone for a given time slot is identified by data written (from time-to-time) into the tone select RAM 135 from a command buffer 15 register 221 which is loaded with tone command signals TC received on conductors TC 0-5. The writing of a tone command signal is to an address which is taken from an address command buffer register 222 through MUX 1 during the time of an RST pulse the register 222 having been loaded by slot command signals SC received on conductors SC 0-4. Loading or--writing"into buffer registers 221 and 222 occurs when a write command signal WC (applied to their terminals W) goes high; otherwise 20 the contained data is always signalled at the outputs of such registers. The conductors TC 0-5, SC 0-4 and WC constitute the command bus CB shown in Figure 1 as extending from the control unit 12 to the tone source 30.

It may be desirable in some cases for the time slots TS,,7-TS47 (which carry switched tones) to be designated numerically in the central control unit 12, and by the signals SC, as channels 0-31 which 25 are available to carry switched tones. For this reason, an adder 225 which always adds sixteen to the number signalled at its input and signals the sum at its output is interposed between the lines SC 0-4 and the input of buffer register 222. Thus, if the slot command signals take on any of values of SC6-SC,, then the corresponding output signals DTS from the buffer register 222 will have -desired time slot- values of DTS,g-13TS47, respectively.

One set of commands to change the switched tone being transmitted in one time slot may be accepted and put into effect during one time cycle or frame. It will thus require six cycles if the control unit calls for changing of six switched tones. But the control unit may issue its command (calling for a given tone to be switched into a given slot) at any time during a cycle, and the command will be put into effect during the reset interval at the start of the next cycle. Because a cycle is 125 iu sec., commands 35 are executed almost instantaneously insofar as human reactions are concerned.

When changing of a switched tone is desired, the controlunit produces a--tonecommand- signal on lines TC 0-5 and a---slotcommand signal- on lines SC 0-4. It simultaneously produces a high level write pulse WC to stobe the signals on those lines respectively into buffers 221 and 222. Assume, as an example, that the control unit 12 sends signals TC2, and SC1, simultaneously with a WC pulse calling 40 for tone TN2. to be preselected for time slot TS,, The write pulse WC causes the numbers "26" and ---33---to be written into the registers 221 and 222, recalling that the adder 225 adds---16---to---17---to produce---33---. The register outputs for the desired tone and the desired time slot (on lines DT 0-5 and DTS 0-5) thus become DT2, and DTS33.

The fact that new command data has been written (at any time during a cycle) is recorded in the 45 timing circuits 36. As shown in Figure 4, the rising edge of the WC pulse- --clocks-a D-type flip-flop 230 to the " 1---state (cooperating flip-flops 230 and 231 normally being in the cleared or---Wstate). The Q terminal of flip-flop 230 thus makes the D terminal of the associated flip-flop 231 swing high, although the second flip-flop is held in its cleared or "0" state by the signal RST which is high except when the signal RST is momentarily high at the beginning of a cycle (see Figures 6A and 613). When the next cycle 50 begins and RST swings momentarily low, the coincident rising edge of signal CLK "clocks" the flip flop 231 to a---1 " state and makes the signal INIT swing high. As shown in Figure 6A, the signal RST reverts to a---1---level 1/2T later, thus clearing the flip-flop 231 so that the INIT pulse is only 1/2T wide.

The INIT pulse clear or resets flip-flop 230 back to its original "0" state, and it is also fed to the OR circuit 82 and to an AND gate 232. The INIT signal, when it appears, signifies that operations should 55 occur to initialize the apparatus for transmission thereafter of the commanded tone in the commanded time slot The operations next to be described all take place during the 1/2T interval when the signal INIT is high:

1. Because a positive-going edge of CLK initiates the INIT pulse, the AND gate 232 of Figure 4 60 produces a tone select write pulse TSW which is essentially 1/2T wide and coincident with the last half of the high pulse in the signal RST. See Figure 6A.

2. The signal TSW is applied to the write enable terminal W of the tone select RAM 135, so that the latter writes the desired tone ID signals DT previously stored in the buffer 22 1.

21 GB 2 076 614 A 21 3. The address to which such writing occurs in the RAM 135 is determined by the then-existing output of MUX 1 on lines CT 0-5. But since the signal RST is high when the signals INIT and TSW occur, MUX 1 is conditioned to send the output of register 222 to the address lines of RAM 135. The signals DTS previously stored in register 222 thus determine where the desired tone signals are written in the RAM 135. If the command information calls for tone TN26 in time slots TS, then "26" will be written into address location---33-, and TN2. will thereafter be the tone which has been preselected to appear in time slot TS33. As soon as the "writing" takes place, the output signals TC immediately represent the newly written value, e.g., "26".

4. Because the RST pulse forms one input to the OR circuit 220, the EnA terminal of MUX 2 is high at this time, so the signals TC (in the example, representing "26") are fed to lines TT 0-5, thereby 10 designating TN26 as the selected tone, and causing ROM's 44 and 45 to produce readout signals identifying the particular sound pattern and schedule which have been paired for tone TN2.. To pursue the example, assume that tone TN.. is made up of sound pattern PT, and schedule SCH1, 5. Since pattern PT, is identified by the numerical signals at lines PA 0- 4, the first sample ROM is addressed with the pattern number "5" (in the present example) and it produces at FS 0-7 signals 15 identifying the first sample address of pattern PT 6. The RST pulse is also applied to the latch register 92 (Figure 5), clearing the latter and making LOL, LOR. LOS all "O's".

7. The RST pulse is also applied to the OR circuit 64 associated with MUX 3 (Figure 213), so the signals at FS 0-7 are applied to the data input of the next sample RAM 50.

8. The signal INIT applied to the OR circuit 82 (Figure 4) while signal CLK is high, triggers the oneshot 84 so that high pulses occur in the CRW and NSW signals. These cause "writing" of data into the next sample RAM 50 and the control RAM 58 at addresses then signalled on lines CT 0-5, i.e., corresponding to the commanded time slot. The data written into RAM 50 represent the first sample address of the pattern (here assumed to be PT4.) for the commanded tone (assumed to be TNA; the 25 data written into the control RAM 58 is 000 (because the signals LOL, LOR, LOS are all 0) even though ROM 56 is then producing characteristic signals SEQ L, SEG R, SEQ S for the selected pattern (PT5).

This is of no consequence, however, because during the ensuing cycle, a downward scan of the selected pattern will begin, starting with the first sample, so the correct all O's values for WDL, WDR, WDS are written into RAM 58.

Thus, during "initialization" which takes place during the RST pulse interval if an INIT pulse appears, the apparatus is conditioned so that on the next cycle the first sample of the pattern for the commanded tone will be fed, during the commanded time slot to the final output bus OB. On subsequent cycles, and during the same time slot, the samples of that pattern will be scanned. Since no TONS or CRCK signal "1" levels are produced during this reset interval, no sample signals are fed to the 35 output bus OB during the reset interval. When "new" command data is written into the tone select RAM 135, it destroys the data previously stored at the commanded address location, so the tone previously being transmitted in the command time slot is replaced with the newly commanded tone.

New command signals and a WC pulse may arrive any time during a cycleexcept during the rest interval. But, of course, if no new command data and a WC pulse are received during a cycle, the INIT 40 pulse does not appear during the next reset interval, and none of the action here described transpires, because the TSW, NSW and CRW signals are not created in coincidence with the RST pulse.

8. Intercept Tones An intercept sound signal (ISS) is one which to the ear gives the impression of two sounds alternating in time (but even that type of tone may have an overriding on/off schedule). The impression 45 is quite similar to the sound of police sirens commonly used in France and other European countries.

The present invention permits various ones of the available tones Ti\1d--TN,, to have ISS characteristics, wherein the two sounds are those formed by two of the initially stored sound patterns. This is accomplished by an extra bit of storage capacity in each word of the select ROM 44, here designated in Figure 2A as bit b, When the ROM is initially "burned" or loaded with data, any tone to be 50 given ISS characteristics has the word at the corresponding address formed with a " 1 " in bit bt;; a "0" at bit b. designates a tone without intercept characteristics.

As an example assume that tone TN4. is to be of an intercept type, and that the word stored at address---43---in ROM 44 is loaded as 101101 (least significant bit on the right) for bits bo-b,. The first five bits numerically represent "13", and when read out onto lines PA 0-4 will normally cause reading 55 of samples from sound pattern PT,3 in the fashion explained above. But the presence of the '1---in bit b, will cause the transmission of sounds SD13 and SI),, during predetermined alternate time intervals, the latter typically being.5 seconds in the manner now to be explained.

If tone TN4. is preselected to be transmitted in slot TSW then when the control signals at CT 0-5 represent "38-, the tone ID signals TI at TT 0-5 will represent---43-, and the pattern ID signals at PA 60 0-5 will be, in binary form, 101101. Assuming that a signal ALT is at b 0 level, the output of an AND gate 240 in an intercept inverter 241 will be disabled (even though the signal at PA 5 is a " 11, so that the signal on line PAO will pass unchanged through EX-OR circuit 48 to form the address bit on conductor A8. So long as this condition prevails, during each occurrence of slot TSW samples will be 22 GB 2 076 614 A 22 outputted by scanning the pattern PT1, stored in TP ROM chip CHP3, and specifically in the second block of word locations on that chip.

But in keeping with the present invention, the signal ALT is made to alternate between high and low levels with half periods substantially greater than the sample scanning rate. For this purpose in the present embodiment, the lowest order stage of the counter 202 (on which appears a squarewave having a frequency of 10 Hz. and a period of 100 m.s.), is connected to supply the input to a "count to 10" counter 244 (viewable also as a frequency divider which divides by 10). The latter at its highest order stage produces the signal ALT as a squarewave of 1 Hz. which is alternately.5 seconds high and a.5 low. Different duty cycles may, of course, be chosen.

During the "high" intervals of the ALT signal, the gate 240 is enabled and transmits the -1- level 10 signal on conductor PA 5 to the EX-OR circuit 48. Therefore, the signal PAO is applied to the address line A8 for alternately.5 seconds "true" and.5 seconds "inverted". This means that during the "true" intervals, successive samples of pattern PT1, are outputted to the bus OB; but during the "inverted" intervals successive samples of pattern PT,2 are outputted, because changing of the signals A8 switches the addressing of the TP ROM chips from one block to the adjacent block but without changing 15 the scanning of samples read from within a block.

In the example here chosen and stated above, therefore, if tone TN43 is initially chosen to be heard as an ISS, and a -1 " is stored in bit b, of word 43 of the pattern select ROM 44, then when that tone is preselected for transmission in a given time slot (say, TS,,), the samples from pattern PT13 will be put out on the bus OB for alternate periods of.5 seconds and the samples from pattern PT,, will be put out 20 on the bus for intervening alternate periods of.5 seconds. As ultimately heard by a listener, the tone TS43 will be two alternating sounds, similar to the effect produced by a French police siren. Any tone which is initially given the ISS characteristic (by storing a -1 " in bit b, of the corresponding word of ROM 44), may also have an overriding longer on/off schedule applied to it by storing appropriate paired data in the schedule select ROM 45, but usually the "continuous on" schedule will be chosen for any 25 ISS tone.

In the present embodiment (but not necessarily in all embodiments) of the invention, the ISS tones must be such that the two patterns for each are stored in adjacent address blocks of the TP memory so that alternating of the A8 address signal switches the readout from one block to an adjacent block.

Moreover, during transmission of an ISS type tone, the first sample ROM 60, sequence ROM 56, logic 30 circuits 55, next sample RAM 50 and so on, all function as if only the pattern numerically represented by the signals at PA 0-4 were being scanned. Therefore, the two sound patterns employed for an ISS type tone must have the same number of samples and the same scan sequence characteristics. This is not a serious limitation upon the choices of the two sounds used to make up an intercept tone.

9. Summary and Review of Operation

A brief overview of the tone source 30 may now be set out.

Ignoring for the moment the on/off scheduling, each tone TN,,-TN47 may be considered as made up by one of a plurality of -sounds- W.-SDn Corresponding to a repeating analog wave, at least a portion of the wave being digitally represented by a set or pattern of samples Sd-Sn stored at addressable locations in a readable main memory, here the TP ROM. The main memory holds a plurality 40 of patterns PT6-PTn. A tone TN. is preselected for a given time slot TS, (of slots TSd-TS4,) by ID signals P] appearing at PA 0-4 during every recurrence of that given time slot and the ID signals in effect are used to create address signals at A8, A9 and CT 1-7 which enable reading of a sample from a preselected pattern PT, which constitutes a part of or forms the tone TN.. Incidentally, in using the symbolisms TS6-TS, TN6-TN., PT6-PT,, it is not intended to indicate that the "n" represents the 45 same quantity in each of the pluralities here referred to. As indicated for the preferred embodiment, for example, there are a plurality of available tones Ti\1d---TN47, but a different plurality of available sounds S13d-SI)., represented by patterns PTd-lPT,,; also, one pattern may contain twenty-one samples S,-S,, and another one hundred-fifty samples SO-SM' The particular sample, within the preselected pattern, read in any given cycle Cj is, however, 50 determined by address signals at AO-A7 during that given time slot. The signals AO-A7 form---this cycle- address numbers corresponding to a sample S,; and during the given slot of the cycle C, they are not only applied to the TP ROM address lines, but they are also used to derive the next cycle address signals to be used in the same slot of the ensuring cycle so that the samples of the preselected pattern are scanned. Thus, as cycles C,, Ci+11 C,,, transpire samples SP Sj+1, Si+ 2 of the perselected pattern PT, 55 for the given time siot are read out to the bus OB, where the symbols j, j+l, j+2 do not necessarily mean that samples are always taken in ascending or descending numerical address order. The next sample address for S,, 1 is written into the Next Sample RAM 50 during cycle C, and then read from RAM 50 and used during cycle C,+1. In this way, the samples of a preselected pattern are scanned seriatim in a pass but the scan fashion of successive passes may be different and the sequence of successive scans may have different characteristics for different patterns. An important key to the advantageous result lie in the use of present sample address signals to derive the proper sample address signals for reading out the next sample during the next cycle. As those skilled in the art will appreciate 23 GB 2 076 614 A 23 from the present teachings, the invention in its broader aspects may also be practiced by saving the address for sample S, used during cycle C, until cycle C,,,, and then in cycle C,+, deriving the address S,+, and using it in cycle C,+,.

The beauty of the apparatus and its method is not only that the samples of a preselected pattern are scanned in a given time slot by progressively changing the reading addresses fed to the TP ROM during that time slot in successive cycles, but also that any pattern may be preselected from any time slot to provide easy switching of different sounds into different time slots by commands received from a control unit. Because the samples are stored in a main memory which is selectively read only during each time slot, rather than for a whole cycle, it is a simple matter to change the "preselection" assignments as to which sound will be transmitted in the slot.

Indeed, and as here described, some of the time slots (TS6--TS,,) may have certain respective tones or sound patterns permanently assigned to them giving what are known as fixed tones. But others of the time slots (TSV_TSJ may carry any desired one of the available plurality of tones or sound patterns.

Each of those latter time slots is identified by a control signal CT,CT17 created by the counter 15 35; and it causes the commanded pattern (that is, one sample of the commanded pattern) to be outputted because it is utilized to read the ID number of the pre- assigned tone TN,, from the tone select RAM 135 whose contents are changeable in response to commands loaded into that RAM from the buffer 221 at a "time slot" address signalled by the buffer 222. The tone ID number TI. identifies the preassigned tone during a time slot; and by working through the ROM's 44 and 45, pattern ID signals 20 Pl,, and schedule ID signals SS are produced during that same time slot, with the samples of the preselected pattern being scanned in successive cycles, and the final output being given an on/off schedule generated at the ROM 200 and selected according to the values of the schedule ID signals SS.

Any of a plurality of sounds SD07-SD3, represented by stored patterns PT6PT,, may be paired with any of a plurality of schedules SCH6-SCH,, stored as the bit sequences in the on/off ROM 200 to 25 provide any of a large plurality of available tones (here TN6--TN47). All schedules are always available as on-going real time on/off signals at the sixteen outputs of the ROM 200; but as each time slot appears in rear time, the signal representing the preselected schedule SCH,, for the perselected tone TN. exerts its overriding control at the final gate 112 so that all or any number of the transmitted tones are eventually heard by a listener with a desired on/off effect.

A tone is earily predesignated to have the intercept sound; the extra ID bit b, in the Pattern Select ROM permits a pattern ID number (in bits b,-b4) to result in alternate outputting (here on a.5/.5 sec.

basis) of one sound corresponding to the identified pattern and a second sound corresponding to the pattern stored in an adjacent block of the TP ROM. A simple alternating of the single address bit signal at A8 results in the changing from one sound to the other.

While preferred embodiments of the method and apparatus have here been disclosed with reference to specific binary signal levels, gate memories and the like, it is to. be understood that many changes in detail may be made as a matter of engineering choices without departing from the scope of the invention as defined by the appended claims. Indeed, those skilled in the art may prefer to embody the apparatus in an iterating microprocessor or digital computer form, and in the light of the present 40 description they will find it easy to implement that choice. Also, it is not necessary to adopt all of the various advantageous features of the present disclosure into a single composite tone source in order to realize their individual advantages. Accordingly, such features are individually defined as sub combinations in some of the claims which follow.

As the last portion of the present specification, the Tables i-Xli referred to above appears below 45 in one place for convenient reference.

24 GB 2 076 614 A 24 TABLE 1

* PA4 PA3 PA2 PAO- 4 TP CHIP CONTENTS OF VALUE ENABLED CHIP 0 0 0 0 to 3 0 Contains PATS. 0-3 0 0 1 4 to 7 1 Contains PATS. 4-7 0 1 0 8 to 11 2 Contains PATS. 8-11 0 1 1 12 to 15 3 Contains PATS. 12-15 1 0 0 16 to 19 4 Contains PATS. 16-19 1 0 1 20 to 23 5 Contains PATS. 20-23 1 1 0 24 to 27 6 Contains PATS. 24-27 1 1 1 28 to 31 7 PATS. 28-31 TABLE 11

SOUND PATTERN CALLED PA1 _.AO VALUE OF A8 & A9 GROUP FOR BY PA0-4 A9 A8 1n AO-9 BLK.

0 0 0 0 0 1 0 1 256 1 2 1 0 512 2 3 1 1 768 3 4 0 0 0 0 0 1 256 1 6 1 0 512 2 - 7 1 - 1 768 ' 3 8 0 0- 0 0 9 0 1 256 1 1 0 512 2 11 1 1 768 "3 12 0 0 0 0 13 0 1 256 1 14 1 0 512 2 L 31 1 1 1 1 11 768 1-- TABLE Ill

255 R LOR CMP AC 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 TABLE IV

255 R FSS 0 0 0 0 1 0 1 0 1 1 0 GB 2 076 614 A 25 TABLE V

255 LOL L WDL 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 1 0 26 GB 2 076 614 A 26 TABLE VI emp 255 LOR R WDR 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 TABLE V1 I

255 L SIG, 0 0 1 0 1 1 0 0 1 1 TABLE VIII

CMP R SIG, 0 0 1 0 1 1 1 0 1 27 GB 2 076 614 A 27 TAE3LE'lX S LOS SIG2 SIG, WDL WDS 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 d o 0 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 01 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 - 1 0 0 0 0 0 1 0 0 1 1 A 0 28 TABLE X EIGHT PATTERN SEQUENCES GB 2 076 614 A 28 SEQ. SEQUENCE NO. CONTROL BITS SAMPLE SEQUENCE L R S 1 0 0 0 2 0 1 0 3 0 0 4 0 0 L L L L L L L L 0 V1 1 6 1 1 0 L L L L 1 7 1 0 1 1 1 1 '1 1 1 W.

+ L -L -L -L -L -L -L -L 8 -L -L 9 -L 1 -L 11 2 29 GB 2 076 614 A 29 TABLE XI

SEQUENCES PRODUCED BY SEQUENCE CONTROL WORDS STORED IN ROM #1 #2 _#3 #4 #5 #6 #7 #8 m R -S L R S L R S L R S L R S- L R S L R S L R S 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 1 1 0 1 0 1 1 1 1 000 000 000 000 000 000 000 000 753 253 -53 7573 F5 3 253 E3 253 000 000 000 000 000 000 20-11 000 254 254 E4 254 254 F54 254 254 000 000 000 00 0 000 000 000 000 255 255 255 255 255 255 255 255 FSS-1 AC-1 WDS=1 WD1_=1 WDR-1 WDR=1 WD1_=1 WDL-1 000 WDR=1 s--s=i ido WDS=1 WD1_=1 WDS-1 WDS-1 FSA 010 001- 75-5 AC=1 AC=1 101 FD -R= 1 000 254 FSA FSS=1 011 110 255 AC-1 FSA+1 AC=1 Los=1 WD1_=0 254 255 D8=1 ill 000 WDR=1 WDS=1 000 AC=1 WDR=1 LOS=1 255 FSA+2 010 001 FSA 011 C=1 FSS=1 WDL-0 253 FSA+1 000 253 010 001 WDS-1 AC=71 LOS-1 FSA+1 AC-1 254 FSA WDR=1 WDR=1 WDS=1 WDR-1 WDS=1 AC=1 41 AC-1 ' c-o -S= 1 oil 001 254 253 FSA+1 AC-1 011 WDR=1 WDS-1 LOS-1 000 001 FSA+1. AC=1 LOS-1 253 010 255 000 AC=1 IFSA+1 L05=1 753 011 AC-1 WDS=O FSA 011 WDR=1 FSS-1 C5P 1 FSA+1 000 AC-0 010 001 AC-1 FSA FSA WDR=0 FSA+1 255 011 CMP-1 000 WDL=O AC-1 WDS=O FSA 7C-0 FSA+1 000 010 WD1_=1 CMP-1 WDR-0 FSA+1 FSA LOS=1 AC-0 000 1 000 CMP=1 100 WDR-0 FSA+1 11 FSA+2 000 255 WDL-0 000 000 FSA+1 WDS=O 000 S-A+2 253 WDL-0 FSA+1 LOS=0 AC-0 000 FSS=1 75-3 000 000 000 253 FSA 253 000 253 000 253 GB 2 076 614 A 30 TAE3LE XI I EXEMPLARY SCHEDULE ROM CONTENTS ADDRESS IN DECIMAL NOS.

STORED DATA b15 1 1 1 1 1 1 1 1 1 1 W 1 1 1 1 1 1 1 1 1 11 l- b4 1 1 1 1 1 1 1 1 1 1 1 W 1 1 1 1 g 1 1 1 1 1 1 1 b2 1 1 1 1 1 1 1 1 1 i 1 bl 1 1 1 1 1 1 1 1 1 1 bO 0 0 0 0 0 0 0 0 0 0 0 79 0 80 1 98 0 99 0 foo 1 0 0 119 0 -' --1-0 1 0 0 1 1 0 0 0 0 1 1 0 1 1 1 1 1 1 '11-, 0 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1. 0 0 0 1 0 0 1 0 31

Claims (9)

1. GB 2 076 614 A 31 1. A method of creating different on/off schedules for a plurality of information signals which are ordinarily transmitted in respective time slots of successive cycles in a multiplex communication system, said method comprising:

   (a) initially storing strings of 0 and 1 bits in an addressable memory for each of a plurality of on/off schedules, each string containing N bits and being characterised by n l's in succession followed by m O's in succession, where n and m are integers including zero but not exceeding N, (b) reading out from said memory simultaneously on plural output lines one bit of each string, and continuing such reading to cyclically scan at a predetermined rate (e.g., one readout per 50 m.s.) all the successive bits of all the stored strings, (c) during certain time slots within successive cycles selecting from the output lines of said memory one readout string of signals, and (d) gating to or blocking from a common output bus the information signals arriving in any given time slot only when the selected readout string of signals has respectively one or the other of its two 15. possible states during that time slot.
2. 2. A method as claimed in claim 1 further characterised in that said cycles have a duration on the order of 12 5,u seconds and the successive reading-out from said memory occurs for intervals on the order of 50 m.s. with negligible spacing between such intervals.
3. 3. A method as claimed in claim 1 further characterised in that said memory contains N addressable word locations, with each word containing one bit of each string, and the cyclical scanning 20 of said step (d) is carried out by driving a digital rollover counter from regularly recurring clock pulses, said counter having N possible count states, and applying the multi-bit output of said counter to the address input lines of said memory.
4. 4. A method as claimed in claim 1 wherein said step (c) includes (c') initially storing a schedule select code in each word location of an addressable schedule- 25 select memory, (c") applying to the address inputs of said schedule-select memory during each of certain time slots within successive cycles address signals which correspond to the particular code for the desired schedule to be created in that time slot, and W9 using the output of said schedule select memory during each time slot to select one string of 30 output signals read out from said string-storing memory.
5. 5. Apparatus for turning a gate on or off according to any one of a plurality of schedules during certain ones of a plurality of time slots in successive cycles in a multiplex communication system, said apparatus comprising, in combination:

   (a) a readable addressable memory storing strings of 0 and 1 bits of data, one string for each of a 35 plurality of schedules SCH.-SCH, each string containing N bits and being characterised by a different combination of n l's in succession followed by m O's in succession, where n and m are integers including zero but not exceeding N, (b) means for reading out from said memory simultaneously on plural output lines one bit of each string, and cyclically scanning the reading through the N bits of the strings at a predetermined rate, and 40 (c) means for applying to the gate, as its control signal, during each occurrence of said certain ones of time slots of every cycle, the signal appearing on a respective preselected one of said output fines.
6. 6. The combination as claimed in claim 5 further characterised in that said cycles have a duration on the order of 125ju sec. and said predetermined rate is on the order of 50 m.s. per bit.
7. 7. The combination as claimed in claim 5 further characterised in that (a') said memory contains N addressable word locations with each word storing one bit of all of said strings, and including (d) a rollover counter driven by clock pulses occurring at a predetermined rate and having N count 50 states per counter cycle, the output lines of the counter being connected to the address lines of said memory.
8. B. The combination as claimed in claim 5 further including:

   (d) a second readable memory storing at different word locations therein different ones of a plurality of schedule ID signals, (e) means for applying to the address lines of said second memory, during each time slot of every cycle, address signals which correspond to the location of the ID signals representing the particular schedule SCH,, desired to be created in that time slot, and (f) means responsive to output signals from said second memory during each time slot for selecting and applying to said gate the corresponding one of the output signals from the first-named 60 memory.
9. 9. Apparatus for turning a gate on or off substantially as hereinbefore described and as shown in the accompanying drawings.

   Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1981. Published by the Patent Office, Southampton Buildings, London, WC2A lAY, from which copies may be obtained.