GB2075225A

GB2075225A - Address range extension

Info

Publication number: GB2075225A
Application number: GB8109571A
Authority: GB
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1980-05-02
Filing date: 1981-03-26
Publication date: 1981-11-11
Also published as: CH654157A5; DE3016952C2; DE3016952A1; GB2075225B

Abstract

The central processing unit (CPU) over a processor-controlled switching system such as a PABX includes an address decoder (5) and switching logic (6) which is activated over an output (a) from the address decoder in response to an address fed to that decoder over an address bus (A). Dependent on data transferred to it over a data bus (D), the logic (6) enables either a first (1) or a second (2) memory. This permits the address range to be doubled without increasing the number of address lines. <IMAGE>

Description

SPECIFICATION Address range extension This invention relates to a circuit arrangement for extending the address range of a computer controlled system.

A known circuit arrangement for directly addres sing a memory by a computer permits the address able memory area to be doubled using a predeter ' mined number of direct address lines (DE-OS 2645 044). Thus sixteen address lines, two times 64K locations can be addressed. To this end, a switching logic is provided which enables one of two memory blocks to be addressed in response to block selection signals provided by a read-only memory in response to a machine instruction. By using a programmable read-only memory, a shift register, and a switching logic, the known circuit arrangement can, for exam ple, address a 128K memory, consisting of a 64K data memory and a 64K program memory, via sixteen address lines.

An object of the invention is to double the address range of a data memory in a simple manner without increasing the number of address lines.

According to the invention there is provided a circuit arrangement for extending the address range of a computer-controlled switching system, includ ing a central processing unit cooperating with at least one program memory and with first and second data memories, one or the other of the two data memories being accessible for executing the programs in the program memory, wherein the central processing unit includes an address decoder and a switching logic and wherein the switching logic is activated by the address decoder in response to an address transferred to the decoder over an address bus and, dependent upon data transferred to it over a data bus, enables either the first data memory or the second data memory.

An embodiment of the invention will now be explained with reference to the accompanying draw ing, which is a block diagram of an embodiment of the invention.

The arrangement shown consists essentially of a central processing unit CPU, which co-operates with a first data memory 1, a second data memory 2, and a a program memory 3. The memories 1,2,3 are connected with one another and with the unit CPU via a data bus D and an address bus A. In addition, the unit CPU is connected to the memories 1, 2, 3 via control lines S1.

The central processing unit CPU includes a proces sor 4, an address decoder 5, and switching logic 6.

The input of the decoder 5 is connected to the address bus A, and that of the switching logic 6 is connected to the data bus D. The decoder 5 has several outputs, via which various devices of the overal control system can be enabled in response to an address applied to the input of the decoder 5. The embodiment illustrated in the drawing shows as much of such a control system as is essential to the invention.

The address decoder 5 can turn the switching logic 6 on via an output a. The data bus D is connected to the switching logic 6 by a line S2, over which the accumulator contents of the processor 4 are transfer- red to the switching logic in response to an "out" instruction. If, for example, the switching log 6 provides a logic 1 at its output u, the data memory 1 is enabled and the data memory 2 is inhibited.

Conversely, when the output u is at logic 0, the data memory 2 is enabled and the data memory 1 is inhibited. If the second data memory 2 is also to be enabled on application of a logic 1 to its enable input E2, an inverter (not shown) is placed ahead of the enable input E2. The signal transferred from the data bus D to the switching logic 6 can be passed by simple logic elements to the output u when the switching logic 6 has been turned on via the output a of the address decoder 5.

If the sequence control instructions are in a problem-oriented programming language and stored as an interpretive code, then programs, interpretive code, and data can each be distributed to an address area of, e.g., 64K, the interpretive code being stored in the first memory 1, for example. As a rule, the data memory 2 is then accessible to the processor because it holds the frequently needed data. Only if parts of the program must access the interpretive code is changeover to the data memory 1 effected. This changeover is performed by the address decoder 5 in conjunction with the switching logic 6 as described above. This arrangement allows a a switching signal to be generated by means of simple switching logic. Conventional complex and expensive "paging" facilities with base registers, adding logic, etc. are not needed for memory addressing, so that circuit complexity is considerably decreased.

Claims

1. A circuit arrangement for extending the address range of a computer-controlled switching system, including a central processing unit cooperating with at least one program memory and with first and second data memories, one or the other of the two data memories being accessible for executing the programs in the program memory, wherein the central processing unit includes an address decoder and a switching logic, and wherein switching logic is activated by the address decoder in response to an address transferred to the decoder over an address bus and, dependent upon data transferred to it over a data bus, enables either the first data memory or the second data memory.

2. An arrangement as claimed in claim 1, and in which one of the two data memories holds rarely needed data, while the other data memory holds frequently needed data.

3. An arrangement as claimed in claim 1 or 2, and in which the data memory holding the rarely needed data is a permanent memory, while the other data memory is used both as a working memory and a permanent memory.

4. A circuit arrangement as claimed in claim 1, 2, or 3, and in which the address ranges of the two data memories are equal.

S. A circuit arrangement for extending the address range of a computer-controlled switching system, substantially as described with reference to the accompanying drawing.