GB2073558A - Dot pattern control system - Google Patents

Abstract

Dot patterns can be stored in an RAM (8) at specified addresses so that they can be read out as individual character units for display on a CRT display unit (15) or printing. Characters and drawings can thus be readily read out seriatim. <IMAGE>

Description

SPECIFICATION Dot pattern control system This invention relates to dot pattern control systems for graphic displays and printers.

When reading the displayed data on the screen of a prior-art graphic display, it is usual to read data as character units by reading character codes or as dot units by reading the onsff state of dots. With this reading system, however, it is impossible to simultaneously read out continuous characters. Also it is impossible to read out a dot pattern consisting of a number of dots such as a drawing, and hence the analysis of such a drawing cannot be obtained.

Further, when displaying a character which is not memorized in a character generator on the screen of a graphic display, it has been in practice to produce that character with a graphic function of the display or specify the dots of the character by coupling programmed data. In either case, considerable man-hour and many memorizes are required.

The invention seeks to improve the aforementioned difficiencies in the prior-art, and its object is to provide a dot pattern control system, which permits the simultaneous reading of a number of dot patterns as individual character units from a screen, thus permitting the analysis of a graphic display from the displayed data and also the reading of continuous characters, i.e., a writing, to be readily obtained.

Another object of the invention is to provide a dot pattern control system, which permits a plurality of given dot patterns as individual character units to be preset in a memory means, and with which desired dot patterns can be read out as individual character units from the memory means for display or printing, thus permitting the display or printing of characters, symbols, drawings, etc. to be obtained very simply and with a very simple construction.

To achieve the above objects, the dot pattern display system according to the invention comprises an output memory for memorizing display data or printing data as dot patterns each of a character unit, means for specifying addresses of the output memory, means for reading out dot patterns as individual character units from areas of addresses specified by the specifying means, and a main memory for memorizing dot patterns read out by the reading means.

With this construction according to the invention, dot patterns can be read out from a screen åt least as individual character units, so that it is possible to readily obtain the anlysis of a graphic display or the like from the displayed data and also read out of a displayed writing. Also, it is possible to preset desired dot patterns in an RAM and read out, when desired, desired dot patterns for display on the screen or printing, thus permitting desired modification of the display or print.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a view showing the circuit construction of an embodiment of the invention applied to a CRT display system; Fig. 2 is a view showing the internal register construction of a CPU 1; Fig. 3 is a view showing the internal construction of an RAM 8 with a showing of an example of the state of storage of data; Fig. 4 is a view showing the internal construction of a video RAM 10; Figs. 5A and 5B show a flow chart illustrating a dot pattern output processing; and Fig. 6 shows a flow chart illustrating a dot pattern input processing.

Now, an embodiment of the invention applied to a CRT display system will be described with reference to the accompanying drawings.

Referring now to Fig. 1, designated at lisa CPU (central processing unit), which controlstheopera- tion of the entire CRT display system and is driven by a clock pulse signal supplied from a clock generator 2. The CPU 1 includes arithmetic circuits and memories required to effect the control. Fig. 2 shows various registers constituting the memories of the CPU 1, namely A, B, C, T, F and V registers. The use of these registers will be described hereinafter.

Designated at 3 and 4 in Fig. 1 are respectively an address buffer and a control buffer. These buffers 3 and 4 respectively memorize address data and control data from the CPU 1 temporarily and couple these data to an address decoder6, an ROM (read only memory) 7, and RAM (random access memory) 8, a CRT controller 9, a video RAM 10 and 110 (inputloutput) controller 11 to be described hereinafter. A data buffer 5 is provided for temporarily storing numeral data at the time of the transfer thereof between the CPU 1 and the circuits 7 to 11. The address data coupled from the CPU 1 through the address buffer 3 to the address decoder 6 serves as chip selection data for the circuits 7 to 11. When this data is decoded in the address decoder,the corresponding circuit is selected.In the ROM 7, in addition to a control program for controlling the entire system, character patterns for characters, numerals, symbols, etc. that are generally capable of display on the screen of the CRT display system are permanently memorized, for instance as respective 7 by 5 dot matrices. When displaying new data on the screen, character patterns for the desired data to be displayed are read out from the ROM 7 according to the address specification from the CPU 1 and written in the video RAM 10. In the RAM 8 data and programs are stored. Also, characters which are not memorized in the ROM 7 can be preset from a keyboard 12 in the RAM 8 and read out therefrom, when desired, for display on the screen. A pattern table for storing dot patterns in the RAM 8 is constituted by the 5,000-th and following addresses as shown in Fig. 3. Data for one byte can be stored in each address.Each of the characters stored in the RAM 8 is a dot pattern based on a 8 by 8 dot mat rices. Fig. 3 shows the state of storage of a dot pattern fora symbol "0". As is shown, the dot pattern for the symbol "0" is constituted by data "11111111" stored in the 5,000-th and 5,007-th addresses and data "10000001" stored in the 5,0001 -st to 5,006-th addresses. In this way, a desired dot pattern can be written in the RAM 8. The dot patterns preset in the RAM 8 can be read out, when desired, for display on the CRT screen. At the time of the reading of a dot pattern or dot patterns, the processing as shown in the flow chart of Figs. 5A and 5B is excuted, as will be described hereinafter.Through this processing, it is not only possible to read out a dot pattern of a single character only from the RAM 8, but is also possible to simultaneously read out a plurality of consecutive character dot patterns from the RAM for display. Further, it is possible to take the OR, AND and exclusive OR of the dot pattern data read out from the RAM 8 and the data having been displayed in the relevant area or areas of the CRT screen and display the resultant dot pattern data in that area or areas. Of course, it is possible to clear data displayed on the CRT display and display the sole read-out pattern data in its place.

The dot patterns read out from the RAM 8 according to the user's instruction or character patterns read out from the ROM 7 according to the instruction .from the CPU 1 are transferred to and written in the video RAM 10. Atthistime, the video RAM 10 is given address specification by address data coupled from the CPU 1 through the address buffer3 and a multiplexer 13. Forthe display of the dot pattern data written in the video RAM 10 and/or character pattern data from the ROM 7 on the CRT screen, the video RAM 10 is caused to execute periodic refreshing operation underthe control from a CRT controller 9.

More particularly, the CRT controller 9 produces well-known horizontal and vertical sync signals, a clock signal and address data. The address data is coupled through the multiplexer 13 to the video RAM 10, the clock signal is coupled to a P-S (parallel-to-serial) converter 14, and the sync signals are coupled to a CRT display unit 15. Thus, the dot pattern data read out from the video RAM andlor character data from the ROM 7, which are parallel data, are converted through the P-S converter into serial data which are coupled to the CRT display unit 15 for display.

According to the invention, the data displayed on the screen of the CRT display unit 15 in the above manner, i.e., dot patterns and character patterns, can be read out as individual character units from the screen and transferred to the RAM 8 for storage therein. In this case, a dot pattern reading processing as shown in the flow chart of Fig. 6 is excuted according to a predetermined instruction given by the user as will be described hereinafter. Through this processing, the data displayed on the screen is handled and processed as dot patterns each of a unit character, and simultaneous reading of a plurality of dot patterns for consecutive characters can be readily obtained.Also, the dot patterns read out from the screen and written in the RAM 8 as individual character units can be processed in the CPU 1, whereby analysis of a graphic display or a writing on the screen can be readily obtained.

The address data produced from the CRT control ler9 mentioned above is also coupled as a key sam pling timing signal to a key controller 16. Thus, the individual keys arranged as a matrix array in the keyboard 12 are scanned according to the address data coupled through the key controller 16 at the time of the key sampling, and a detection signal rep resenting the on-off state of the individual keys, which is obtained as a result of the scanning, is cou pled through the key controller 16 and CRT controller 9 to the CPU 1 and processed there. The I/O control ler 11 is a control unit for controlling the data transfer between an external unit 17 such as a printer and the CPU1.

Fig. 4 outlines the internal construction of the video RAM 10. As is shown, the video RAM 10 has a screen construction consisting of 16 character rows each consisting of 32 character areas. The individual character areas are given respective cursor addres ses "0" to "511". Each character area, which is specified by a corresponidng cursor address, has a dot matrix configuration consisting of 8 dots by 8 rows. Thus, according to the invention each character displayed on the screen can be dealt with as a dot pattern of one character unit. The construction of the screen of the CRT display unit 15 has a one-to-one correspondence to the screen construction of the video RAM 10. The video RAM 10 may have any desired structural relation to the RAM 8.

Now, the operation of the above embodiment will be described. In the first place, the operation in case when presetting a character, symbol or the like, which is not stored in the ROM 7, in the RAM 8 as a dot pattern of one character unit will be described.

When storing a dot pattern of a symbol, for instance "O", in the 5,000-th whroug h 5,007-th addresses of the RAM 8 in the manner as shown in Fig. 3, a prog ram AS= "11111111"+"1 0000001"+ "10000001"+ . . .

+ "11111111" is coupled. Likewise, data for dot patterns to be stored in the 5,008th and following addresses of the RAM 8 are coupled one byte in each row after another. When coupling the aforementioned program, address data, control data and numeral data, respectively having predetermined contents, are produced from the CPU 1 and coupled to the address buffer 3, control buffer 4 and data buffer 5, respectively. As a result, data is written in the RAM 8 one byte after another with the chip selection effected according to the output of the address decoder, the write command given according to the output of the control buffer4 and address specification effected according to the outputs of the address buffer 3 and data buffer 5.

Now, the operation in case when displaying the dot pattern (i.e., symbol "[1") in the 5,000-th through 5,007-th addresses in the RAM 8 on an area of the CRT display (for instance with cursor "32"), on which data (for instance representing the English letter A) is being displayed by the previous process, will be described with reference to the flow chart of Fig. 5. In this case, the given data are coupled while the cursor is displayed on the cursor address "32" on the screen according to the program given as GOUTA$ (F, N) (1) where F specifies either one of data "0", "1" and "2".

When F = "0", it sepcifies that the data (for a dot pattern) from the RAM 8 be directly displayed. When F = "1 ", it specifies that the data having been displayed on the screen and that the data pattern from the RAM 8 (i.e., dot pattern) be both displayed as their OR. When F = "2", it specifies that of the previous data on the screen and the data from the RAM 8 (i.e., dot pattern) common dots be displayed as the AND of these data. In formula (1), N is the number of characters (i.e., dot patterns) to be read out from the RAM 8.

In the instant case, the symbol "Cl" is to be read out from the RAM 8 for display in the area of the cursor address "32", so N="1".Also, F = "1 " for it isto be displayed by the OR display. The data F = "1" is written in the F register (Fig. 2) in the CPU 1.

Underthe control by the CPU 1,the processing of Fig. 5 is started, and a first step S, is executed. In the step S1, the cursor address "32" is multiplied by 8 to obtain a video pointer "256", which is stored in the V register (Fig. 2) in the CPU 1. This video pointer gives address data for the video RAM 10. Then, in a step 82 the programmed data N = "1" is coupled to the C register (Fig. 2), and in a step S3 the data "1" in the C register is multiplied by 8to obtain data "8", which is stored again in the C register.In a subsequent step S4, the 5,000-th address, which is the leading address in the pattern table, is coupled as input data to the T register (Fig. 2) in the CPU 1 and stored there as a table pointer specifying the address in the RAM 8.

Then, in a step S, whether N = "0" is checked. In the instant case N = "1", so thatthe processing goes to a step S6, in which the data "11111111 " in the 5,000-th address of the pattern table as specified by the content of the table pointer is read out and transferred to the A register (Fig. 2) in the CPU 1 to be stored therein. In a subsequent stepS7, "1" is subtracted from the data N = "8" in the C register, and the result "7" is written again in the C register. Then, in a step S8 the content of the data F is checked in the CPU 1.In the instant case, F = "1", so that the processing goes to the stepS8, in which data in the address of the RAM 10 specified by the video pointer "256" is read out and transferred to the B register (Fig. 2) to be stored therein. In the subsequent step St0, the OR of the data in the A register and the data in the B register is taken, and the result is stored in the A register again. In the subsequent step Sii, the aforementioned result stored in the A register is written in an area of the video RAM 10 having addresses specified by the video pointer "256". Then, "1" is added to the video pointer in a step S,2, and also "1" is added to the table pointer in a step S12, and also "1" is added to the table pointer in a step S,3.As a result, the video pointer is stored as "257" in the V register, and the table pointer is stored as "5001" in the T register. In a subsequent step S14 whether the content of the table pointer has advanced by an amount corresponding to one character is checked.

Since the answer in this step is "NO" at this time, the processing returns to the step Ss. Through the above operation, data obtained as the result of taking the OR of the data "11111111 " in the 5,000-th address in the RAM 8 constituting the dot pattern and the data in the first row of the area specified by the video pointer "256", i.e., the area of the cursor address "32", is written in the area of the video RAM 10 specified by the video pointer "256".

After the excution of the step S,, the stepS, of reading out the data "10000001" in the 5,001-st address of the RAM 8 and storing it in the A register is executed. Then, the steps S7 through S13 are executed, whereby the data obtained as a result of taking the OR of the data in the 5,001-st address of the RAM 8 and the data in the second row of the area with the cursor address "32" stored in the RAM 10 is written in the second row of the area of the RAM 10 with the cursor address "32", i.e., the video pointer "257". Afterthe step S14, the processing returns to the step Ss.

When the OR data of the data in the 5,002-nd to 5,007-th addresses in the RAM 8 on one hand and corresponding data in the rows stored in the addresses of the video RAM 10 specified by the pointers 258 to 263 are subsequently calculated and written in the areas specified by the video pointers "258" to "263" through the repetition of the steps Ss through 813, in the next step S14 it is determined that the processing with respect to the aforementioned symbol "O" specified by the table pointer is ended. Then, the processing goes to a step S1, in which whether N = "0", i.e.,whetherthe processing with respect to all the characters is ended, is checked.Since in this case N = "0" after the repetition of the step S7 eight times, the entire processing is ended. In this way, the data for the symbol "eel" stored in the RAM 8 is displayed in the area with the cursor address "32" in the CRT display unit 15 together with the English letter "A" which has previously been displayed alone in that area; in other words, the resultant OR data, namely a dot pattern "eel" is newly displayed.

When it is desired to display the AND data of the data in the RAM 8 and the data in the video RAM 10 on the screen of the CRT display unit 15 of this embodiment F = "2" is coupled instead of F = in the program of the formula (1). In this case, after a step S16 which is the same as the stepS, in the case of the OR data display, the AND of the two data is taken in a step S17r so that only the common dots in the dot pattern of the aforementioned symbol "eel" and that of the English letter "A" are displayed in the area of the cursor address "32". Also, with N = "0" coupled when coupling the program of formula (1), a step Si, is executed after the stepS,. Namely, in the step Si, data "0" is written in the A register. In this case no data is read out from the pattern table in the RAM 8, so that the display is unchanged in the case of the OR data display and vanishes in the case of the AND data display. Further, by coupling F = "0" when coupling the program of formula (1), the step S" is excuted after the step S,. In this case, like the prior -art CRT display system the dot pattern (i.e., symbol "eel") from the pattern table is written in the area with the cursor address "32" in the video RAM 10, so that the English letter"A" which has been displayed in the area with the cursor address "32" of the CRT display is cleared and the symbol "eel" is displayed in the place.

When data "2" or greater is coupled as N at the time of coupling the program of formula (1), a dot pattern in the 5,008-th and following addresses is read out, whereby data obtained through the processing in the flow chart of Fig. 5 is similarly displayed in each of the areas with the cursor address "32" and following cursor addresses in the CRT display 15. In this way, by setting data "2" or greater as N, a plurality of consecutive dot patterns can be simultaneously read out from the RAM 8 for display as OR data or AND data on the CRT display 15.

Now, the operation when reading out data on the screen of the CRT display 15 and transferring these data to the RAM 8 for storage therein will be described with reference to Fig. 6. In this case, the given data are coupled according to a program GlNA$(X,N) (2) where X is the cursor address of the video RAM 10, and N is the number of characters to be read out.

When transferring the dot pattern (I.E., symbol "eel") displayed in the area of the cursor address "32" to the pattern table of the 5,000-th and following addresses in the RAM 8, "32" is coupled as data X and "1 " as data N at the time of coupling the program of formula (2).

When the processing shown by the flow chart of Fig. 6 is started, the data X is coupled to the A register in a step S21, and it is multiplied by 8 to obtain data "256" which is stored in the A register in a step 822. Then, the data N is coupled to the B register in a step S23, and it is multiplied by 8to obtain data "8" which is stored in the B register in a step S2+ In a subsequent step 82,, the 5,000-th address which is the leading address of the pattern table is stored as table pointer"500" in the T register.Then, in a step S26 data "11111111 " is read out from the address of the RAM 10 specified by the data "256" in the A register and transferred to the A register for storage therein, and in a step 827,1" is added to the data in the A registerto obtain data "257" which is written in the A register. Subsequently, in a step 828 the data "11111111" in the C register is read out and written in the area of the RAM 8 with the address specified by the table pointer "500" in the T register, and in a step S29 "1" is added to the table pointer to obtain a pointer "5001". In a subsequent step S30, "1" is added to the data in the B register to obtain data "7" which is written again in the G register.Then, whether the data in the B register is "0", whetherthe reading process with respect to the symbol "eel" is completed, is checked in a step S. Since the answer is "NO" atthistime,the processing is returned to the step 828. When the process of steps S26 through 821 is subsequently repeated seven times, the dot pattern forthe symbol "eel" displayed in the area of the cursor address "32" in the CRT display 15 is entirely written in the 5,000-th to 5,007-th addresses specified by the RAM 8.

In case when simultaneonsly reading out a plurality of consecutive data in areas of cursor addresses following the cursor address "32" and transferring them to 5,008-th and following addresses of the RAM 8, data "2" or greater may be coupled as data N atthe time of coupling data according to the program of formula (2). The data, i.e., image information, read out and written in the RAM 8 in the above way, can be processed for various analyses in the CPU 1.

While the above embodiment has concerned with a CRT display system, the invention is also applicable for use with various other data output systems such as printers.

Claims (3)

1. A dot pattern control system comprising an output memory for memorizing display data or printing data as dot patterns each of a character unit, means for specifying addresses of said output memory, means for reading out dot patterns as individual character units from areas of addresses specified by said specifying means, and a main memory for memorizing dot patterns read out by said reading means.

2. A dot pattern control system comprising a memory means for memorizing dot patterns each of a character unit, means for reading dot patterns memorized in said memory means as individual character units, and means for displaying or printing dot patterns read out by said reading means.

3. A dot pattern control system, substantially as hereinbefore described with reference to the accompanying drawings.