GB2064868A - Schottky barrier gate field-effect transistor - Google Patents
Schottky barrier gate field-effect transistor Download PDFInfo
- Publication number
- GB2064868A GB2064868A GB8037089A GB8038990A GB2064868A GB 2064868 A GB2064868 A GB 2064868A GB 8037089 A GB8037089 A GB 8037089A GB 8038990 A GB8038990 A GB 8038990A GB 2064868 A GB2064868 A GB 2064868A
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- walls
- layer
- active layer
- schottky barrier
- electrode metal
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- 230000004888 barrier function Effects 0.000 title claims abstract description 23
- 230000005669 field effect Effects 0.000 title abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000007738 vacuum evaporation Methods 0.000 claims abstract description 15
- 239000011810 insulating material Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 30
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 229910052681 coesite Inorganic materials 0.000 description 11
- 229910052906 cristobalite Inorganic materials 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 11
- 235000012239 silicon dioxide Nutrition 0.000 description 11
- 229910052682 stishovite Inorganic materials 0.000 description 11
- 229910052905 tridymite Inorganic materials 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910000990 Ni alloy Inorganic materials 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/061—Manufacture or treatment of FETs having Schottky gates
- H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
In a method of manufacturing a Schottky barrier gate field-effect transistor, an electrically conductive active layer 7 is formed on a semi-insulating semi-conductor substrate 6, two adjacent walls 8, 9 of insulating material are formed on the active layer 7 so as to extend linearly parallel to one another, an ohmic electrode metal is then vacuum-evaporated obliquely with respect to the upstanding surfaces of the two walls 8 and 9 to form ohmic electrodes layers 10, 11 on the active layer 7 in areas except for that lying between the two walls 8, 9, the layer 12 of Schottky barrier metal is subsequently deposited between the two walls 8, 9, whereafter the walls are removed to remove the layers of ohmic electrode metal and Schottky barrier forming metal on the two walls 8, 9. Alternatively the walls are composed of a resist layer and an insulating film, and the resist layer with the electrode metal thereon is removed directly after vacuum-evaporation of the electrode metal. <IMAGE>
Description
SPECIFICATION
A method of manufacturing semiconductor devices
The present invention relates to a method of manufacturing semiconductor devices.
A schottky barrier gate field-effect transistor (hereinafter referred to as a "MES FET" when applicable) employs a Schottky barrier for its gate electrode which is formed by depositing metal in contact with a semi-conductor surface. MES FETs are extensively employed in low-noise amplifiers, high-output amplifiers or oscillators in the range of microwave frequencies.
Figures lA-iD show the manufacturing steps used in a conventional MES FET manufacturing method.
As shown in Figure 1A, an active layer 2 is formed on a semi-insulating semi-conductor wafer 1 be epitaxial growth. The region of the active layer 2 is limited to a desired extent by mesa etching as seen in
Figures 1 B. In Figure 1 C, a source electrode 3 and a drain electrode 4 are formed with Au-Ge-Ni alloy using ordinary vacuum evaporation and lithography techniques and thereafter the wafer is subjected to heat treatment at 4700C for several minutes. Then, a gate electrode is formed in a region of the active layer 7 between the source electrode 3 and the drain electrode 4 using ordinary vacuum evaporation and lithography techniques.
In order to improve the high frequency response of a MES FET, it is necessary to make the gate length as short as possible. Accordingly, the element must be manufactured with considerably high precision.
In the conventional manufacturing method described above, in the formation of the pattern of the gate electrode 5 using photoresist material (hereinaftertermed simply "resist") steps. are formed in the vicinity of the gate pattern by the source electrode 3 and the drain electrode. Accordingly, the resolution of the gate pattern is not so good as would have been the case had the patterns been formed on a flat surface. Thus, it is difficult to form a gate pattern as short as 1 Fm with the conventional manufacturing method. In addition, while it is necessary to form the gate electrode with a high alignment accuracy of the order of +0.2 lim between the source electrode 3 and the drain electrode 4 which were previously formed, it is difficult using known techniques to locate these electrodes with such a high accuracy.Accordingly, the conventional manufacturing method provides a very low manufacturing yield.
Usually in the manufacture of devices of this type, a method is employed in which, prior to the formation of the gate electrode 5, the source electrode 3 and the drain electrode 4 are subjected to an alloying treatment to reduce the contact resistance thereto. However, if the heat treatment is carried out at a sufficiently high temperature for a long time, metal cohesion or balling-up occurs in the source and drain electrodes, which increase the magnitude of the steps in the vicinity thereof. This is one of the factors which adversely affects the resolution of the gate photoresist pattern.
Accordingly, an object of the invention is to alleviate or overcome the above-descibed drawbacks accompanying conventional methods of manufacturing semiconductor devices.
The foregoing object of the invention is achieved by the provision of a semiconductor device manufacturing method in which two adjacent walls are formed on an electrically conductive active layer provided on a semiconductor substrate and a vacuum evaporation angle is suitably selected so that electrode metal is vacuum-evaporated on desired regions only of said active layer.
More specifically, the invention resides in one aspect in a method of manufacturing a semiconductor device comprising the steps of:
forming an electrically conductive active layer on a semi-insulating semiconductor substrate;
forming two adjacent walls on said active layer which extend linearly parallel to one another;
vacuum-evaporating an ohmic electrode metal obliquely with respect to the upstanding surfaces of said two walls to form a layer of ohmic electrode metal selectively on said active layer except for region of said active layer between said two walls;
depositing a layer of Schottky barrier metal on said region of said active layer between said two walls; and
removing said two walls to remove said laayers of ohmic electrode metal and Schottky barrier metal formed on said two walls.
The walls may be formed of a resist material or a combination of resist material and an insulating material which serves as a spacer. Alternatively, the walls may be entirely of an insulating material.
In a further aspect, the invention resides in a method of manufacturing a semi-conductor device comprising the steps of:
forming an electrically conductive active layer on a semi-insulating semiconductor substrate;
forming two adjacent walls on said active layer extending linearly parallel to one another, each of said two walls comprising an insulating film and a resist layer;
vacuum evaporating an ohmic electrode metal obliquely with respect to the upstanding surfaces of said two walls to form a layer of ohmic electrode metal on said active layer except for a region of said active layer between said two walls;
removing each resist layer to remove said layer of ohmic electrode metal formed on each resist layer;
heating said layer of ohmic electrode metal;
depositing a layer of Schottky barrier metal on said region of said active layer between said two insulating films; and
removing each insulating film to remove said layer of Schottky barrier metal formed on each insulating film.
The angle of vacuum evaporation for depositing the layer of Schottky barrier metal may be varied from the vertical in order to produce a shorter gate electrode. Prior to vacuum-evaporating the Schottky barrier metal, the surface of the semiconductor substrate may be etched to form a gate electrode therein. After the two walls have been formed, the surface of the semiconductor substrate may be mesa-etched.
In the accompanying drawings;
Figures lA-ID are explanatory diagrams showing the manufacturing steps in a conventional semiconductor device manufacturing method;
Figures 2A-2Fand 3 are explanatory diagrams showing the steps in a semiconductor device manufacturing method according to a first example of the invention;
Figures 4 and 5 are diagrams illustrating methods according to second and third examples respectively of the invention; and
Figures 6A-6/are explanatory diagrams showing the manufacturing steps in a method according to a fourth example of the invention.
The invention will be described with reference to its preferred embodiments. A variety of materials may be used to form the walls. First, examples of a method of the invention in which resist is used to form the walls will be described.
Referring to Figure 2, in the method of the first example an n-GaAs active layer7 is formed on an upper surface of a semi-insulating semiconductor crystal substrate 6, such as GaAs, as shown in Figure 2A. In this formation, a vapor-phase epitaxial growth method is preferably employed although a liquidphase epitaxial growth method or an ion implantation method may alternatively be employed. Thereafter, the n-GaAs active layer 7 is limited to the desired region by mesa-etching as shown in Figure 2B.
Next, resist walls 8 and 9 are formed on the active layer 7 parallel to and adjacent to each other and extending linearly on the surface of the semiconductor substrate as shown in Figure 2C. In this case, as the surface of the active layer 7 is accurately flat, the resist walls 8 and 9 can be formed with a high precision. That is, a precise pattern can be formed to the extent of 1 Ftm for instance.
Thereafter, as shown in Figure 2D, an ohmic electrode metal such as Au-Ge-Ni alloy is vacuumevaporated in two oblique directions to form ohmic electrode layers selectively on regions of the active layer 7 (except for a gate region) which are outside the resist walls 8 and 9, thus forming a source electrode 10 and a drain electrode 11.
In order that only the regions of the active layer 7 outside the resist walls 8 and 9 are subjected to vacuum evaporation and the region between the resist walls 8 and 9 is not so subjected, an advantageous vacuum evaporation angle must be determined. This angle can be determined by elementary geometry or from a diagram. For instance, in the case where the walls 8 and 9 and 1 um in height and are spaced 1 um from each other, it is necessary that the vacuum evaporation angle be more than 45 with respect to a normal to the upper surface of the substrate. However, the walls are not always uniform in height and distance. Therefore, it is desirable that the vacuum evaporation angle is more than 65 .
If it is difficult to sufficiently increase the ratio of the height of the walls to the width using only the resist layer, the vacuum evaporation angle must be relatively large and accordingly the resultant layer will be smaller in thickness. This difficulty can be overcome by employing the following method. An insulating layer serving as a spacer is formed using
SiO2, Si3N4 or polyimide resin below the resist layer and then the insulating layer thus formed is subjected to chemical etching, plasma etching or ion etching using the resist layer as a mask to form the sufficiently high walls.
Then, as shown in Figure 2E, Schottky barrier metal such as aluminum is vacuum evaporated substantially perpendicularly to the upper surface of the substrate to form a Schottky gate electrode 12 upon the active layer 7 between the resist walls 8 and 9. In this step, alminum is vacuum-evaporated onto the active layer 7 outside the resist walls 8 and 9 as well. However, the aluminum layers are isolated from the regions of the active layer 7 because of the presence of the Au-Ge-Ni alloy layers. That is, as the aluminum layers are merely deposited on the Au
Ge-Ni alloy layers, the ohmic characteristics thereof are changed very little.
Finally, the resist walls 8 and 9 are removed and the wafer is subjected to a heat treatment at a temperature of about 470 C for several tens of seconds to thereby obtain an excellent ohmic characteristic. The device thus formed has a MES FET structure as shown in Figure 2F.
Figure 3 shows the positional relationships of the electrodes produced in the course of manufacturing the semi-conductor device as described above. In
Figure 3, the hatched portion indicates regions where the resist material is present over the active layer and reference numerals 8 and 9 designated the adjacent resist walls. Further in Figure 3, reference numeral 13 designates a gate region. As the gate region 13 is surrounded by the resist walls 8 and 9, no ohmic electrode metal is deposited in the gate region 13 when the ohmic electrode metal is vacuum evaporated is described before. Two layers of ohmic electrode metal and Schottky barrier metal are formed over the entire region except the gate region 13. However, when the resist is removed, the metal layers on the resist are removed together with the resist.As a result, the source electrode 10, the drain electrode 11, the Schottky gate electrode 12, and a pad 14 coupled to the gate electrode are left with their configurations defined as shown in Figure 3.
Referring to Figure 4, in the second example, the vacuum-evaporation angle of the Schottky barrier metal is controlled to obtain a gate length which is shorter than the distance between resist walls 8 and 9. The vacuum-evaporation angle is varied freely to the extent that a Schottky gate electrode 12 is formed upon the surface of an active layer 7 which is located between the resist walls 8 and 9 whereby a
MES FET can be manufactured whose gate length is significantly shorter than can be obtained using ordinary lithography techniques.
As is apparent from the above description, the semi-conductor device manufacturing method according to the invention is quite broad in its application and can be changed or modified in various ways. For instance, after the step of vacuumevaporating the ohmic electrode metal outside the resist walls 8 and 9 (Figure 2D) has been accomplished, a step of lightly etching the exposed surface of the active layer 7 between the resist walls 8 and 9 may be carried out. In this case, in the resulting structure, as shown in Figure 5, only the portion of the active layer which is under the Schottky gate electrode 12 is of reduced thickness. The MES FET thus formed is advantageous in that its source series resistance is small.
Another example of a method according to the invention, in which two layers, namely, a resist layer and an insulating layers are employed for forming the walls, will now be described with reference to
Figure 6. As shown in Figure 6A, first, an n-GaAs active layer 7 is formed on one surface of a semi-insulating GaAs substrate 6, for instance by a vapor-phase epitaxial growth method, to a thickness of 0.2 um with a carrier density of, for example 1 x 10-17 cm-3. In this growth the dopant material, may, for instance be Te.
As shown in Figure 6B, the region of the active layer 7 is defined as desired. Then, an insulating layer 8 such as an SiO2 layer is formed on the active layer 7 by a low temperature CVD method using SiH4 gas. The thickness of the SiO2 layer 8 is, for instance,
5000#.
Thereafter, as seen in Figure 6D, a positive type photoresist is coated over the SiO2 layer 8 to a thickness of 5000 and resist patterns 9 and 10 are formed using conventional techniques as shown in
Figure 6D. The photoresist patterns 9 and 10 extend in a linear pattern on the surface of the semiconductor substrate and are spaced from each other by 1 Fm for instance. The patterns thus formed have an excellent resolution because they are formed on a flat surface.
Then, the SiO2 layer 8 is etched with the resist patterns as a mask to produce two adjacent walls 11 and 12 composed of the SiO2 layers 8a and 8b and the resist patterns 9 and 10 are formed. In this example, electrode metal is vacuum-evaporated selectively by utilizing the two walls 11 and 12 as described below.
First, in order to form a source electrode 13 and a drain electrode 14, an ohmic electrode metal such as
Au-Ge-Ni alloy is vacuum-evaporated obliquely onto the substrate surface to form layers of Au-Ge-Ni alloy upon the active layer 7 outside the two walls 11 and 12. Next, as shown in Figure 6G, the resist patterns 9 and 10 are removed thereby also removing the Au-Ge-Ni alloy layers on the resist patterns 9 and 10. The semiconductor device thus formed is subjected to a heat treatment at 4700C for about two minutes in H2 atmosphere thereby improving the ohmic characteristics of the source electrode 13 and the drain electrode 14.
Thereafter, as shown in Figure 6H, Schottky barrier metal such as aluminum is vacuum-evaporated over the entire surface of the element, thus an aluminum layer is formed upon the active layer 7 between SiO2 layers 8a and 8b to form a Schottky gate electrode 15. In this step, aluminum layers are formed outside the SiO2 layers 8a and 8b. However, as the aluminum layers are merely deposited on top of the
Au-Ge-Ni alloy layers, they do not greatly affect the ohmic characteristics thereof.
In order to more positively electrically insulate the electrodes of the semiconductor device and to increase the manufacturing yield, the following method may be employed. The SiO2 layers 8a and 8b are removed by etching with an ordinary buffer etchant. As a result, the aluminum layers 16 on the
SiO2 layers 8a and 8b are also removed thus providing a MES FET having a sectional structure as shown in Figure 61.
According to this example, the ohmic contact of the drain is subjected to a heat treatment before the formation of the Schottky gate. Therefore, without affecting the electrical characteristics of the Schottky gate the heat treatment can be carried out at a high temperature for a long period of time, and the ohmic characteristics of the resulting device are excellent.
Furthermore, no additional step of forming resist patterns is required after the source electrode 13 and the drain electrode 14 have been heat-treated.
Accordingly, even if balling up were to occur in the source and drain electrodes as a result of the heat treatment, the accuracy of the following precise processing would not be affected. Thus, the source and drain electrode metal can be subjected to heat treatment satisfactorily and the ohmic characteristics are improved.
In accordance with the invention, as described above, two adjacent resist walls are provided on the semiconductor layer and the vacuum evaporation angle is suitably selected so that the electrode metal is vacuum evaporated onto desired regions only.
Accordingly, the source, drain and gate electrodes are formed self aligned. Thus, the method according to the invention is advantageous in that the manufacturing procedure is simple because of the unnecessity for an alignment procedure. Furthermore, as the resist pattern are formed on a flat surface, the resolution of the resist pattern is considerably high.
This is another advantage of the method of the invention. Accordingly, MES FETs having a short gate length can be readily manufactured with a high yield. Thus, the method of the invention can be effectively applied to the manufacture of MES FETs or integrated circuits including MES FETs.
In the above-described examples, the semiconductor material in GaAs. However, it may be InP or another suitable semiconductor material. In addition, the Schottky barrier metal is not limited to aluminum and may be Ti, Cr, Mo orTa. Also, the insulating film is not limited to SiO2 and may be a polyimide resin film or a compound film.
Claims (12)
1. A method of manufacturing a semiconductor device comprising the steps of:
forming an electrically conductive active layer on a semi-insulating semiconductor substrate;
forming two adjacent walls on said active layer which extend linearly parallel to one another;
vacuum-evaporating an ohmic electrode metal obliquely with respect to the upstanding surfaces of said two walls to form a layer of ohmic electrode metal selectively on said active layer except for region of said active layer between said two walls;
depositing a layer of Schottky barrier metal on said region of said active layer between said two walls; and
removing said two walls to remove said layers of ohmic electrode metal and Schottky barrier metal formed on said two walls.
2. A method as claimed in Claim 1, in which said walls comprise resist material.
3. A method as claimed in Claim 1, in which said walls comprise resist material and an insulating material serving as a spacer.
4. A method as claimed in Claim 1, in which said walls comprise an insulating material.
5. A method of manufacturing a semiconductor device comprising the steps of:
forming an electrically conductive active layer on a semi-insulating semiconductor substrate;
forming two adjacent walls on said active layer extending linearly parallel to one another, each of said two walls comprising an insulating film and a resist layer;
vacuum evaporating an ohmic electrode metal obliquely with respect to the upstanding surfaces of said two walls to form a layer of ohmic electrode metal on said active layer except for a region of said active layer between said two walls;
removing each resist layer to remove said layer of ohmic electrode metal formed on each resist layer;
heating said layer of ohmic electrode metal;
depositing a layer of Schottky barrier metal on said region of said active layer between said two insulating films; and
removing each insulating film to remove said layer of Schottky barrier metal formed on each insulating film.
6. A method as claimed in any preceding Claim, in which, in the step of depositing said layer of
Schottky barrier metal, the angle of vacuum evaporation is varied.
7. A method as claimed in any preceding Claim, in which, before vacuum evaporating said Schottky barrier metal, the surface of said semiconductor substrate is etched to form a gate electrode therein.
8. A method as claimed in any preceding Claim, in which, after said two walls have been formed, the surface of said semiconductor substrate is mesa etched.
9. A method as claimed in any preceding claim, wherein the angle of vacuum-evaporation of the ohmic electrode metal is greater than 65" with respect to a normal to the upper surface of said substrate.
10. A method as claimed in Claim 1, of manufacturing a semi-conductor device substantially as hereinbefore described with reference to Figures 2A-2F and 3 or Figure 4, or Figure 5 of the accompanying drawings.
11. A method as claimed in Claim 5, of manufacturing a semi-conductor device substantially as hereinbefore described with reference to Figures 6A-61 of the accompanying drawings.
12. A semi-conductor device manufactured by a method as claimed in any preceding claim.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10141579A | 1979-12-10 | 1979-12-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2064868A true GB2064868A (en) | 1981-06-17 |
| GB2064868B GB2064868B (en) | 1983-12-14 |
Family
ID=22284529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8037089A Expired GB2064868B (en) | 1979-12-10 | 1980-12-04 | Schottry barrier gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2064868B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0091548A2 (en) * | 1982-04-05 | 1983-10-19 | International Business Machines Corporation | Semiconductor structure comprising a mesa region, process for forming a semiconductor mesa; vertical field effect transistor and method of forming a vertical semiconductor device |
| US4587540A (en) * | 1982-04-05 | 1986-05-06 | International Business Machines Corporation | Vertical MESFET with mesa step defining gate length |
| GB2218568A (en) * | 1988-05-13 | 1989-11-15 | Mitsubishi Electric Corp | Production method for semiconductor device |
| GB2262105A (en) * | 1991-12-03 | 1993-06-09 | Marconi Electronic Devices | Manufacturing circuit components by depositing material at an angle on contoured surface |
-
1980
- 1980-12-04 GB GB8037089A patent/GB2064868B/en not_active Expired
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0091548A2 (en) * | 1982-04-05 | 1983-10-19 | International Business Machines Corporation | Semiconductor structure comprising a mesa region, process for forming a semiconductor mesa; vertical field effect transistor and method of forming a vertical semiconductor device |
| EP0091548A3 (en) * | 1982-04-05 | 1986-02-12 | International Business Machines Corporation | Semiconductor structure comprising a mesa region, process for forming a semiconductor mesa; vertical field effect transistor and method of forming a vertical semiconductor device |
| US4587540A (en) * | 1982-04-05 | 1986-05-06 | International Business Machines Corporation | Vertical MESFET with mesa step defining gate length |
| GB2218568A (en) * | 1988-05-13 | 1989-11-15 | Mitsubishi Electric Corp | Production method for semiconductor device |
| US4902646A (en) * | 1988-05-13 | 1990-02-20 | Mitsubishi Denki Kabushiki Kaisha | MESFET process employing dummy electrodes and resist reflow |
| GB2218568B (en) * | 1988-05-13 | 1993-01-20 | Mitsubishi Electric Corp | Semiconductor device and production method therefor |
| GB2262105A (en) * | 1991-12-03 | 1993-06-09 | Marconi Electronic Devices | Manufacturing circuit components by depositing material at an angle on contoured surface |
| GB2262105B (en) * | 1991-12-03 | 1994-11-23 | Marconi Electronic Devices | Method of manufacturing circuit components |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2064868B (en) | 1983-12-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19961119 |