GB2062349A

GB2062349A - Mosfet

Info

Publication number: GB2062349A
Application number: GB8034309A
Authority: GB
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1979-10-30
Filing date: 1980-10-24
Publication date: 1981-05-20
Also published as: DE3039803A1; JPS5673472A; IT1133869B; SE8007492L; YU278180A; FR2469003A1; IT8025290A0

Abstract

A Mosfet having minimized parasitic bipolar effects comprises a substrate having a surface at which source and drain regions (10, 6) are spaced so as to define a channel portion (25) in a body region. The channel portion is formed in a relatively low conductivity portion (22) of the body region, the remainder (24) of the body region being of higher conductivity. A gate 12 overlies the channel portion, and the source electrode (18) also contacts the higher conductivity body portion (24). The device may also be constructed as a VMOS. <IMAGE>

Description

SPECIFICATION Mosfet Device The present invention relates generally to metal oxide semiconductor field effect transistors (MOSFETS) and more particularly to vertical, grooved MOSFET (VMOS) devices, and vertical, double diffused MOSFET (VDMOS) devices.

A typical MOSFET structure comprises a semiconductor substrate which includes adjacent source, body and drain regions of alternate (i.e., P or N) conductivity type. In a vertical MOSFET the source and drain regions are on opposite semiconductor major surfaces and yield a vertical current flow (perpendicular to the surfaces) through the device. In a VDMOS device the semiconductor substrate is substantially planar in configuration. The body region is adjacent to one of the planar surfaces and the gate, comprising an electrode disposed over an oxide, is disposed on the surface over the body region. In a VMOS structure a groove in one of the semiconductor surfaces intersects the body region, and the gate is disposed within the groove over the body region.

When a VDMOS or VMOS device is appropriately biased, majority charge carriers flow from the source, through a channel (in a surface portion of the body region under the gate), to the drain. The device is thus unipolar in nature.

However, the existence of PN junctions between the source and body and between the body and drain create the possibility for minority charge carrier flow (i.e., a parasitic bipolar transistor) as well. Since the efficiency of the unipolar MOSFET is degraded by this bipolar transistor it is desirable to minimize the minority carrier flow. The present invention provides a vertical MOSFET structure having minimized parasitic bipolar effects.

The present MOSFET device comprises a semiconductor substrate including, in series, adjacent source, body and drain regions of alternate conductivity type. The substrate includes a surface at which the source and drain regions are spaced so as to define a channel portion in the body region. The channel portion of the body is of relatively low conductivity compared to the remainder of the body, which has a substantial portion of higher conductivity. A gate is disposed on the channel portion; a source electrode contacts the source region and remainder portion of the body region; and a drain electrode contacts the drain region.

In the drawings: Figure 1 is a sectional view of a VDMOS device embodying the present invention; and Figure 2 is a sectional view of a VMOS device embodying the present invention.

Referring to Figure 1, a VDMOS device 3 of the present invention is shown. The device 3 comprises a substantially planar semiconductor substrate 1 having first and second opposing major surfaces (5 and 7, respectively). For clarity in the drawings, semiconductor regions have been identified as being of N or P type, however, it should be recognized that the device 3 would also be functional if each of these conductivity types was reversed. A drain region 2 is adjacent to the second surface 7 and extends to the first surface 5. In the preferred embodiment the drain region 2 comprises a substantially planar portion of relatively high conductivity 4 at the second surface 7, and an extended drain portion 6 of relatively low conductivity which is disposed across the high conductivity portion and extends to the first surface 5.A pair of body regions 8, spaced apart by the extended drain 6, extends into the substrate from the first surface 5 such that each body region forms a PN junction 28 with the drain 2. Each body region 8 further comprises a relatively low conductivity region 22 adjacent to the extended drain 6 at the first surface, and a higher conductivity region 24 occupying its remainder. A corresponding pair of source regions 10 extend into the substrate from the first surface within the boundaries of the body regions 8, each forming a PN junction 26 with a body region. The source regions 10 are located with respect to the extended drain region 6 between the pair of body regions 8 so as to define the respective lengths of a pair of channel portions 25 at the first surface of each relatively low conductivity body region 22.

In the VDMOS device 3 a gate 12 is disposed on the first surface 5 over both the pair of channel portions 25 and the extended drain region 6 between the channel portions 25. In the preferred embodiment the gate 12 comprises an oxide 14 on the substrate surface 5 and an electrode 16 over the oxide. A pair of source electrodes 18 contacts the first surface 5. Each source electrode 18 corresponds to a source region 10 and electrically shorts a source/body junction 26 at the first surface 5. A drain electrode 20 disposed on the second semiconductor surface 7 contacts the drain region 2. When a voltage exceeding a threshold voltage (VT) is applied to the gate electrode 16, it induces a conduction path in each of the relatively low conductivity body regions 22 and creates a source to drain current from both source regions 10.The depth of each conduction path defines the depth of each channel portion 25 within each low conductivity, body region 22.

Generally, the threshold voltage for a MOSFET device is dependent upon the charge carrier concentration in the channel portion(s) of its body region(s) (V,arbody concentration ] 112). Since device sensitivity is increased by minimizing the threshold voltage, it is desirable to reduce the conductivity of the body region(s). However, a problem occurs in that if the conductivity of an entire body region is minimized, the resulting enhancement in sensitivity is offset by a commensurate increase in parasitic bipolar effects.

The body region of a MOSFET device corresponds to the base of a parasitic bipolar transistor. The parasitic effects arise by virtue of minority carrier flow across the source/body and body/drain PN junctions and can occur whenever a source/body junction is forward biased in the .6-.8 volt range. The presence of bipolar parasitics reduces the breakdown voltage of the device by causing premature avalanching at the body/drain junction. To minimize bipolar effects, the conductivity (i.e., majority carrier concentration) in the body region should be relatively high. This will effectively reduce the gain (which is inversely proportional to the carrier concentration in the base) of the bipolar transistor. A conflict therefore exists in that increasing the conductivity of the body to reduce parasitics reduces the sensitivity of the device as well.

To reduce the bipolar parasitics without degrading the device sensitivity, the present invention utilizes body regions 8 each having both a relatively low conductivity region 22 and a higher conductivity region 24. By locating the gate 12 over the relatively low conductivity body regions 22 the objective is to have the channel portions 25 formed entirely within these low conductivity regions to thereby minimize the threshold voltage of the device. By providing the higher conductivity region 24 in the remainder of each body, the bipolar parasitics are reduced as well. In addition to reducing the gain of the parasitic bipolar transistor, the existence of higher conductivity body region 24 means that charge carriers moving through each body (from drain 2 to source 10) will produce a lower voltage drop, and thus be less likely to forward bias the source/body junction 26.

Furthermore, in the present invention each source electrode 18 is formed so as to contact both a source region 10 and a higher conductivity body region 24. By shorting these two regions, the likelihood of the source/body junctions 26 becoming forward biased is greatly reduced, and the bipolar parasitics are therefore further minimized.

The fabrication of a VDMOS device thus described can be achieved by methods commonly used in the semiconductor industry. For example, starting with a semiconductor substrate which includes a high conductivity layer and a low conductivity epitaxial layer, the relatively low conductivity body 22, higher conductivity body 24 and source 10 regions can be conventionally pattern generated and diffused.

Referring to Figure 2, a VMOS device 33 of the present invention is shown. The device 33 also comprises a substantially planar substrate 30 having first and second opposing major surfaces (35 and 37, respectively). A substantially planar drain region 32 is adjacent to the second surface 37, and in the preferred embodiment comprises a relatively high conductivity portion 34 at the second surface, and a relatively low conductivity extended drain 36 disposed across the high conductivity portion. A body region 38 extends into the substrate from the first surface 35 so as to form a PN junction 48 with the drain region 32.

In the VMOS device 33 a groove 42 extends into the substrate from the first surface 35 so as to intercept the body region 38. A pair of source regions 40 extend into the substrate from the first surface 35, each being adjacent to the groove 42 at the first surface and forming a PN junction 46 with the body region 38. Each of these source regions 40 is spaced from the extended drain region 36 so as to define the length of a channel portion 55 at the groove surface of the body region 38. It should be noted that in the preferred embodiment the groove 42 is V-shaped and may be generated by anisotropically etching the substrate 30. However, the groove shape is not so limited in the present invention. For example, the groove might have a curved (e.g.U-shaped) profile, a generally rectangular profile (with walls perpendicular to the semiconductor surface 35), or a substantially V-shaped profile with a flat (i.e.

parallel to semiconductor surface 35) bottom surface.

A gate 44 is disposed on the surface of the groove 42 and comprises an oxide 47 over the channel portions 55, and an electrode 49 over the oxide. Generally, the oxide 47 and electrode 49 layers of the gate 44 can be continuous across the groove surface. A pair of source electrodes 58 short the source/body junctions 46 at the first semiconductor surface 35, and a drain electrode 50 contacts the drain region 34 on the second semiconductor surface 37.

The principles of operation of the VMOS device 33 are substantially similar to those of the VDMOS device 3. The basic distinction is that in the VDMOS device the gate is located on a major semiconductor surface, such that channel portions are induced in those portions of the body regions at the major semiconductor surface. In the VMOS device the gate is located on a groove surface and induces channel portions in those portions of the body at the groove surface.

For the reasons discussed with reference to the VDMOS device 3, the VMOS embodiment of the present invention also comprises a body region 38 having a relatively low conductivity region 52 and a higher conductivity region 54, such that the channel portion 55 is formed within the relatively low conductivity region. In the VMOS device 33 the relatively low conductivity region 52 is adjacent to the groove 42 and a pair of higher conductivity regions 54 extends from the first surface 35 such that the groove extends between the higher conductivity regions. This device can also be made using conventional pattern generation and diffusion techniques.

Claims

1. A MOSFET device having minimized parasitic bipolar effects, comprising: a semiconductor substrate including, in series, adjacent source, body and drain regions of alternate conductivity type, and having a surface at which the source and drain regions are spaced so as to define a channel portion in the body region; the channel portion being of relatively low conductivity compared to the remainder of the body region; a gate disposed on the channel portion; a source electrode contacting the source region and the remainder of the body region; and a drain electrode contacting the drain region.

2. The device of Claim 1, wherein the device is a vertical MOSFET, comprising: a substrate having first and second opposing major surfaces; the source region, and the body region adjacent to the first surface; and the drain region adjacent to the second surface and extending to the first surface so as to define the channel portion at the first surface.

3. The device of Claim 1, wherein the MOSFET is a VDMOS device comprising: a substrate having first and second opposing major surfaces; a drain region adjacent to the second surface and extending to the first surface; a pair of body region, spaced apart by the drain region, extending into the substrate from the first surface; and a pair of source regions, each extending into the substrate from the first surface within the boundaries of a body region, the pair of source regions defining a pair of channel portions at the first surface with the drain region located therebetween.

4. The device of Claim 3 wherein the drain region further comprises: a substantially planar region of relatively high conductivity adjacent to the second semiconductor surface; and an extended drain region of low conductivity disposed across the planar region and extending to the first surface.

5. The device of Claim 3, further comprising: a gate disposed on the first surface, comprising an oxide disposed over the pair of channel portions and the drain region therebetween, and an electrode disposed on said oxide; a pair of source electrodes, corresponding to the pair of source regions, disposed on the first surface; and the drain electrode disposed on the second surface.

6. The device of Claim 1, wherein the MOSFET is a VMOS device, comprising: a substrate having first and second opposing major surfaces; a groove in the first surface; and the channel portion along a surface of the groove.

7. The device of Claim 6, wherein: the groove is substantially V-shaped.

8. The VMOS device of Claim 6, further comprising: a substantially planar drain region adjacent to the second surface; a body region extending into the substrate from the first surface; the groove within the boundaries of the body region; a pair of source regions at the first surface, each being adjacent to the groove at the first surface; and a gate on the groove surface, comprising an oxide disposed over the body region and an electrode disposed on the oxide.

9. A device of Claim 8 wherein the body region further comprises: a relatively low conductivity region adjacent to the groove; and a pair of higher conductivity regions extending into the substrate from the first surface, the groove being between said pair.

10. The device of Claim 8 wherein the drain region further comprises: a substantially planar region of relatively high conductivity adjacent to the second surface; and a substantially planar extended drain region of lower conductivity disposed across the relatively high conductivity region.

11. The device of Claims 4 or 10 wherein: the extended drain region is an epitaxial layer.

12. A method for fabricating a VMOS device having minimized parasitic bipolar effects, comprising: providing a semiconductor substrate having first and second opposing major surfaces including therein: a substantially planar first conductivity type drain region at the second surface; a substantially planar first conductivity type extended drain region of lower conductivity than the drain region disposed across the drain region; and a second conductivity type body region adjacent to the extended drain region; generating a first conductivity type source region extending from the first surface within the boundaries of the body region; forming a two layer structure over the source region, said structure comprising a secondary mask layer over a primary mask layer; forming a pair of relatively high conductivity body regions, of lower conductivity than the source region, in those areas not covered with the two layer structure, said relatively high conductivity body regions extending from the first surface to approximately the same depth as the lower conductivity body region and diffusing laterally beneath the two layer structure a predetermined distance;; undercutting the secondary mask layer a distance greater than said lateral diffusion distance so as to yield the secondary mask layer overhanging the primary mask layer; stripping the secondary mask layer; forming a third mask layer in areas not covered by the primary mask layer; stripping the primary mask layer; forming a groove in the area not masked by the third mask layer, so as to expose the relatively low conductivity body; and generating a gate oxide on the exposed body region in the groove, a gate electrode on the gate oxide, a drain electrode on the drain region at the second surface, and a source electrode on the source region and relatively high conductivity body regions at the first surface.

13. The method of Claim 12 wherein the method for forming the two layer structure comprises: sequentially forming the primary and secondary mask layers; and selectively removing both layers.

14. The method of Claim 12 wherein: the primary mask layer is SiO2; the secondary mask layer is Si3N4; the third mask layer is thermally grown Six, or sufficient thickness to withstand the stripping of the primary mask layer; and the secondary mask layer is stripped after the third mask layer is formed.

15. The method of Claim 12, further comprising: thermally growing a SiO2 fourth mask layer on the first surface prior to forming the two layer structure; forming the third mask layer by thermally growing SiO2; and removing that portion of the fourth layer which underlies the primary layer after the primary layer is stripped.

16. The method of Claims 12 or 15 wherein: the primary mask layer is Si3N4; and the secondary mask layer is SiO2.

17. The method of Claims 12 or 15 wherein: the primary mask layer is Si3N4; the secondary mask layer is photoresist; and the undercutting of the photoresist is performed by plasma etching.

18. The method of Claim 12 further comprising: forming a fourth mask layer on the first surface prior to forming the two layer structure; removing those portions of the fourth mask layer which are not covered by the primary mask layer, following the stripping of the secondary mask layer; stripping the primary mask layer prior to forming the third mask layer; and stripping the fourth mask layer after forming the third mask layer.

19. The method of Claim 18 further comprising: forming the fourth mask layer coincident with the two layer structure.

20. The method of Claims 18 or 19 wherein: the fourth mask layer is Si3N4; the primary mask layer is SiO2; and the secondary mask layer is Si3N4.

21. The method of Claims 18 or 1 9 wherein: the fourth mask layer is Si3N4; the primary mask layer is SiO2; and the secondary mask layer is photoresist.

22. The method of Claims 1 5, 18 or 19 wherein: the distance of undercutting is substantially equal to the lateral diffusion distance of the relatively high conductivity body regions.

23. A MOSFET device as claimed in claim 1, substantially as described herein with reference to Figure 1 or Figure 2 of the accompanying drawings.

24. A method as claimed in claim 12, substantially as described herein.