GB2054226A - Transmitters and receivers for the transmission of parallel data in serial form - Google Patents

Abstract

A data transmission system in which a multiplexer scans a plurality of switches under the addressing control of a parallel binary output of a counter driven by clock pulses. If any switch is closed, the counter is stopped temporarily and a UART is loaded with the particular parallel binary output. The counter is restarted to continue the search whilst the UART transmits a serial form of the said output down a single channel. The UART thus transmits signals which repeatedly identify in sequence those switches which are closed. <IMAGE>

Description

SPECIFICATION Transmitters and receivers for the transmission of parallel data in serial form This invention relates to the transmission in serial form of data which is presented in parallel form.

The invention is particularly intended for use in conjunction with the scanning of a multiplicity of selectively actuable inputs, such as switches, to detect the states of those switches, and to transmit information which identifies those switches which are in a particular state along a single channel to a receiver with which the serial information is reconverted into a form corresponding to that of the inputs. One particular example of the use to which the invention may be put is in the remote control of a vehicle by means of a single channel such as coaxial cable, balanced twin feeder cable or a radio link. For the control of a vehicle there may be, at a controller, a large number of switches, the states of which determine the functions which the vehicle is to perform.In general, any or all the switches may be in a particular state and it has hitherto proved difficult to devise a transmission system which can transmit information efficiently when only a few switches are in the predetermined state yet can continue to operate conveniently when a large number of switches are in the predetermined state.

It has been proposed, in for example British Patent Specification No. 1492376 to scan a multiplicity of inputs cyclically, to form a code identifying an active input and to transmit that code in serial form. However, the system described in that specification is unsuitable for use when more than one input is active at any particular time.

In its broadest form, the present invention provides a data transmitter which includes a multiplicity of selectively actuable inputs.

These inputs may be represented by a multiplicity of switches. A clock controlled counter or other suitable means provides a cyclic sequence of parallel binary words each of which constitutes an address for a respective one of the inputs so that the inputs can be scanned one at a time under the control of the words which are provided in sequence. When an input is detected to be in a predetermined state, represented for example by the closure of the respective switch, the multiplexer or other scanning means provides a control which temporarily stops the progression of the cyclic sequence of words. The parallel binary word which is provided at that time is fed into a parallel-to-serial converter, which is preferably constituted by a UART (universal asynchronous receiver and transmitter) which thereafter transmits the word in serial form.

Once the word has been fed into the UART or other converter, the progression of the sequence of words may restart.

As will be more fully apparent from the following description, the continuance of the search is not dependent on the cessation of the predetermined state of an input of which the address has been fed to the converter.

Another feature of the invention resides in the facility for rapid and repeated transmission of data relating to the respective inputs when only a small number out of the total number of inputs are likely to be active at any time. It is readily possible to ensure, by an appropriate choice of clock frequency for the said sequence, that the cyclic searching sequence proceeds such that normally serial data is fed out from the UART or other converter at the maximum possible rate.

The invention includes within its scope a data transmission system which includes a transmitter as set forth above and a receiver, which may comprise a UART and a binary addressed multiplexer, for converting the transmitted serial data into a parallel form that reproduces the signal pattern at the aforementioned inputs.

In the accompanying drawings: Figure 1 illustrates schematically a data transmitter; Figure 2 illustrates a known form of UART; and Figure 3 illustrates a receiver.

The transmitter shown in Fig. 1 includes a multiplicity of selectively actuable inputs represented by the switches 1. Conveniently there are 2" inputs, so that the address of any input may be represented by an n-bit parallel binary word. At any time any or all of the switches may be closed; for convenience it will be presumed that the predetermined state which it is desired to detect corresponds to the closure of a switch.

A clock pulse generator 2 generates clock pulses, which may be at, for example, a frequency of 2 MHz. These clock pulses fire a monostable multivibrator 3 which drives a binary counter 4. The binary counter provides at any time an output, on a bus 5 in the form of an n-bit parallel binary word. As the counter progresses through a counting sequence of 2", the binary words occur one at a time in cyclic progression. The words are received one at a time by a binary addressed multiplexer 6, which scans the switches one at a time so that the particular switch which is scanned is determined by the word which constitutes the output of the counter at that time. The multiplexer is arranged to provide, on an output line 7, a control signal should the switch which is scanned at any given time be in the predetermined (closed) state.

The parallel data bus 5 extends to the input of a UART 8 so that the word which is at any particular time presented to the multiplexer is also presented to the UART 8.

The control signal which appears on the line 7 serves two purposes. First, it inhibits the monostable 3 so as, temporarily, to stop the flow of pulses from the clock pulse generator 2 to the binary counter 4. Second, it enables the loading of the UART with the parallel binary word that is presented on the bus 5.

As will be explained with reference to Fig.

2, the UART will, once it is loaded, proceed to feed out in serial form a coded signal corresponding to the parallel word that it has received. The rate at which the serial information is fed out from the UART is determined by a secondary clock signal which is obtained from a divider 9 that receives the clock pulses from the generator 2. The particular frequency of the secondary clock pulses is not important and in practice may vary between 500 Hz and 1 25 kHz. Typically it may be 64 kHz which is, in accordance with the ordinary operation of a UART, sixteen times the rate, 4 kHz, at which serial data is fed out from the UART.

This data is fed to a terminal 10 which may be connected via a transmission link such as a coaxial cable, to a receiver as is described later with reference to Fig. 3.

Once the UART has been loaded, the scanning of the inputs may recommence. A UART normally has a terminal which can indicate when the UART has been loaded and this terminal may be connected, by means of a line 11, to the monostable 3 to remove the inhibit which has been provided by the signal on line 7. Thereupon the counter may restart so that the search for the next active input may recommence.

Fig. 2 illustrates in a simplified manner for the purpose of illustration a known form of UART. The UART has an input parallel data bus 20 which can feed an input register, normally termed transmitter holding register 21. The UART has a transmitter shift register 23 which is under the control of timing and control circuits 24 that receive a clock input 25. The UART includes, in its transmitter section, a control register 26, which determines the mode of operation of the transmitter section and a parity generator 27; these two parts are not relevant to understanding the present invention.

If the UART receives an appropriate input at the terminal 22, the register 21 can be loaded from the bus 20. Thereafter, provided that the shift register 23 is vacant, the contents of the register 21 may be transferred to the shift register 23. The contents of the shift register are shifted out, in serial form, at a rate which is determined by, and is normally onesixteenth of the rate of the clock pulses at the clock input 25.

Those skilled in the art will understand that data words cannot be loaded into the register 21 more quickly than the shift register 23 clears and it may happen, particularly if a large number of the switches 1 are closed, that a word is presented on the bus 20 and an enabling input is received at the terminal 22 while the shift register 23 is not yet empty. Should this happen, the loading of the next word must await the clearing of the register 23 and the immediately subsequent loading of the register 23 with the contents of register 21. During the slight delay, the progression of the counter 4 will be temporarily interrupted, but the count will restart as soon as the register 21 has been loaded.

Although the use of UART is particularly convenient for the conversion of parallel data into serial data and its transmission asynchronously with its reception, it is feasible to use, instead of a UART, a different parallel to serial converter which performs the essential functions of the registers 21 and 23. The use of a UART is not essential to the present invention but it has the advantages of commercial availability and the automatic generation of parity checks.

The right-hand part of Fig. 2 illustrates the receiving section of the typical UART. It includes a serial data input 28 for a receiver shift register 29, which is controlled by a timing and control circuit 30 which receives a clock input at a terminal 31. The receiving section further includes a receiver holding register 32, a set of drivers 33, an output bus 34 and a status register 36 which is of no consequence to the present invention. The operation of the UART as the receiver is, briefly, as follows. Data is received at the input 28 and is shifted into the register 29 at a rate determined by the control 30 and derived from the clock input (31).As the shift register 29 is filled, the contents thereof are transferred to the holding register 32 and subsequently operate the drivers 33 so as to provide on the lines of the output bus 34 a parallel signal corresponding to the respective part of the serial signal received at the input 28.

Fig. 3 illustrates a receiver for use in cooperation with the transmitter shown in Fig. 1.

In the receiver, a UART 41, arranged in the receiving mode receives a clock signal from a clock pulse generator 42 by way of a divider 43. This clock signal should be nominally at the same frequency as that which controls the UART 8 but need not be linked to it. The UART 41 generates the same n-bit words as were loaded in sequence in to the transmitting UART and feeds those words in succession on an output bus to a binary addressed multiplexer 44 which provides a logic 1 signal on a particular one of 2n lines corresponding in number to the switches 1. These lines are connected to a respective one of a set of integrators 45 which hold the logic state of the respective lines for an appropriate time, for example corresponding to a period greater than the maximum time between successive interrogations of the same input so that if a switch should remain continuously closed, the output on the respective output line of the integrator remains continuously active.

The various output lines of the integrator each control a respective function in a function control unit 46 of which the operation is of no consequence to the present invention.

It should be noted that if there are separately grouped functions to be controlled, for example main functions on a vehicle and other functions on an associated equipment, two or more receiving UARTS may be used and the respective receivers could be provided with channels only for the respective functions controlled by the individual UART. Where the invention is used for the remote control of vehicles, this expedient avoids the need for multiway connectors between remote parts of a vehicle.

The described system has several advantages in practice. It may employ standard computer interface units. It combines the fast search mode with a slow transmit mode and in general enables optimum use of the available bandwidth of the transmission link. It does not require close synchronisation of the receiver and transmitter. In normal use only a few commands, represented by active inputs, will be made at any one time and can be transmitted quickly yet the system can accommodate a very large number of commands if necessary. Finally, the system can readily be provided in modular form and can be expanded to a considerable size.

Claims (3)

1. A data transmitter comprising a multiplicity of selectively actuable inputs, means for providing a cyclic sequence of parallel binary words each constituting an address for a respective one of said inputs, means under the control of the successive binary words to scan the respective inputs one at a time and to provide a control signal on the detection of a predetermined state of any input in its turn, a parallel to serial converter which can receive the current word in response to the control signal and can thereafter transmit the data word in serial form, and means for interrupting temporarily the progression of the said sequence during the reception of the said word by the converter; whereby the transmitter provides a serial output which repeatedly identifies in sequence the inputs which are in the predetermined state.

2. A data transmitter comprising a multiplicity of switches, a clock controlled counter for providing a cyclic sequence of parallel binary words each identifying one of said switches, a multiplexer for scanning one switch at a time in response to the said words, means for temporarily stopping the counter in response to detection of a predetermined state of any switch when it is scanned, a universal asynchronous receiver and transmitter (UART), means for causing the loading of the UART with the word corresponding to the scanned switch during the cessation of the count, and means for applying a clock signal to the UART to cause it to provide a serial data transmission of each word with which it is loaded, whereby the UART transmits signals which repeatedly identify in sequence the switches which are in the predetermined state.

3. A data transmission system comprising a data transmitter acording to claim 1 or claim 2 and a receiver which comprises means arranged to receive serial data from the transmitter, means for converting the serial data into outputs on lines corresponding to the said inputs or switches, and an integrator for each of the said lines.