GB2037128A - Electronic telephone on a chip - Google Patents

Abstract

An electronic telephone wherein the functions of maintaining a balanced impedance, detecting the presence of a ring, generating the ring, and sharing a common pair of wires for both transmittal and reception without excessive feedback are electronically synthesized so as to replace electromechanical and other non-electronic components typically employed. Digital switching techniques are employed to perform the hybrid coupler function, thereby eliminating the need for a phase inversion transformer which is otherwise typically used. A totally integrated one chip telephone is thereby provided, wherein low cost switching circuits may be employed as a replacement for all transformers, and both FET and bipolar techniques are utilized so as to enable significant size reduction in capacitors. The electronic telephone may be equipped with a push-button keyboard pad for interconnection of the dialling function to the external common wire pair.

Description

SPECIFICATION Electronic telephone on a chip Background of the Invention This invention generally relates to a telephone set and, more particularly, to a wholly electronic telephone wherein electro-mechanical and other non-electronic components commonly employed in a standard telephone are replaced by electronic circuitry such that a totally integrated one chip telephone is provided.

A transmission medium of telephone communication typically includes a wire line system which comprises pairs of wires, each pair handling bidirectional communications thereupon. Each telephone instrument used in the wire line system is connected to a two-wire pair, and must provide a current path of twenty milliamperes (approximately), detect ringing signals, transmit (or send) voice signals, and receive voice signals. In the transmission and reception of signals along the same pair of wires, excessive feedback (also referred to as side-tone) must be prevented.

Heretofore, an arrangement including two transformers and a cancellation mode commonly called a hybrid coupler has been employed to control feedback, and therefore was not reducible to integrated circuit form.

Summary of the Invention In accordance with this invention, an electronic telephone capable of being integrated onto a single semiconductor chip is provided which includes a line balancing-buffering external connection circuit, a ring detectiongenerating circuit, and a digital hybrid circuit.

The external connection circuit provides the proper interface to the central telephone switching office line pair. The digital hybrid circuit functions as a four wire to two wire interface, connecting the transmitter and receiver from the telephone handset to the same wire pair by alternatingly placing sample increments of data from the transmitted signal and received signal onto the signal wire pair, operating at a frequency faster than the human ear can detect so as to effectuate nondetectable signal reconstruction, while maintaining isolation between the receiver and transmitter so as to eliminate excessive feedback therebetween.The external connection circuit also functions to detect the activation of the hook switch signifying the telephone is in use, and in response to an activation signal, places a suitable impedance in parallel with the external line pair to create a suitable current loop load in compliance with the telephone communications and carriers requirements.

Brief Description of the Drawings The aforementioned and other features, characteristics, and advantages and the invention in general, will be better understood from the following more detailed description taken in conjunction with the accompanying drawings in which: Figure 1 is a block diagram illustrating an electronic telephone as constructed in accordance with the present invention; Figure 2 is a detailed block diagram of the electronic telephone illustrated in Fig. 1; Figure 3 is a partial schematic/partial block diagram showing one embodiment of the external connection circuit of Fig. 1; Figure 4 is a block diagram of a digital hybrid coupler as constructed in accordance with the present invention and forming a component of the electronic telephone as shown in Fig. 1;; Figure 5 is a schematic block diagram illustrating a preferred embodiment of the digital hybrid coupler shown in Fig. 4; Figures 6A and 6B are alternate embodiments of the transmitter gating means and receiver gating means as included in the digital hybrid coupler of Fig. 4, while Figure 6C is an alternate embodiment of the voltage divider as included in the digital hybrid coupler of Fig. 4; Figure 7 is a block diagram of the digital hybrid coupler as shown in Fig. 4, but illustrating another embodiment of the transmitting switch and receiving switch; Figure 8 is a circuit diagram showing the impedance/switch network of Fig. 2.

Detailed Description of the Drawings Referring to Fig. 1, a block diagram of the electronic telephone 10 is shown. Fig. 1 shows the functional subelements required for the electronic telephone 1 0. Terminals 11 and 1 2 are connected to the external connection circuit 20 wherein the functions of maintaining a balanced impedance, isolation, and current loop generation are performed. A ringing circuit 21 is connected to the external connection circuit 20, via conductor 22, which performs the functions of ringing signal detection and transformation to an appropriate form so as to generate an audible signal in response to the detection of the ringing signal.External connection circuit 20 is connected to an automatic switching digital hybrid circuit 23, comprised of a low pass network filter 24, a sending circuit 25, a receiving circuit 26 and a switching circuit 36. External connection circuit 20 is connected to a low pass filter 24 via conductors 30 and 31. The low pass network filter 24 is connected to the sending circuit 25 and the receiving circuit 26 via conductors 32 and 33. Thus the sending circuit 25 and receiving circuit 26 are connected through the low pass network filter 24, through the external connection circuit 20, back to the terminals 11 and 12 which are for connection to the central system wire pair. Sending circuit 25 selectively conducts signals from a transmitter 35, via conductors 34 connecting the transmitter 35 to the sending circuit 25, to the low pass network filter 24.

This selective gating of the transmitter signal in the sending circuit 25 is accomplished in response to an enabling signal from the switching circuit 36 which is connected via conductor 37 to the sending circuit 25. In an alternating-exclusive-or manner, the switching circuit 36 alternately enables the receiving circuit 26 via conductor 38 to allow passage of an incoming signal to a receiver 41 via conductor 40. The enabling signals from the switching circuit 36 are such that either the sending circuit 25 is enabled or the receiving circuit 26 is enabled, but never both simultaneously. Thus for sequential time periods, the signals passing through terminals 11 and 1 2 will be of the form: transmitted signal, received signal, transmitted signal, received signal, etc.

Referring now to Fig. 2, a detailed block diagram of an electronic telephone 10 is shown as in Fig. 1. Terminals 11 and 1 2 provide for connection to the external wire line system of the central telephone switching system. Terminals 11 and 1 2 are also connected to the inputs of a steering circuit 43, that may take the form of a diode, which polarizes and feeds through the incoming signals, as well as allowing transmitted outgoing signals to pass therethrough back to terminals 11 and 12. Polarized signals are output on conductors 44 and 45 which are connected to an impedance/switch network 50, to a regulator 51, to a differential input amplifier 52 and a differential output amplifier 53. Conductor 44 is also connected to the input of a low pass ringing filter 54.The ringing filter 54 is selective so as to only allow the low frequency, 20 Hz, and relatively high voltage, 100V, ring signal to pass to a ring processor 59 via a conductor 55. The ring processor 59 detects the presence of a ringing signal, and upon detection, outputs a signal of suitable form to an internal ringer output 56, or for connection to a ringer output connection 57 via conductor 58. The ringer output connection 57 provides a point for connection to an externally supplied external ring output 60 which may consist of a bell ringer, a piezoelectric annunciator, or other electronically activated means. The internal ringer output 56 may optionally provide the ringing function as a part of the electronic telephone itself. The steering means 43 may be formed as a biased junction or diode, and as such may be reduced to integrated circuit form.The ringing circuit 21 of Fig. 1 is comprised of the low pass ringing filter 54, the ring processor 59, the internal ringer output 56, and the ringer output connection 57.

Polarized signals from the steering means 43 pass through conductors 44 and 45 to the differential input amplifier 52 and the differential output amplifier 53. The differential input amplifier 52 maintains a balanced load to the external wire pair via conductors 44 and 45, feeding back therefrom to terminals 11 and 12, and provides electrical isolation between its inputs and its output. The output of the differential input amplifier 52, i.e. the incoming signal, is connected to a low pass network filter 70 via conductor 66. The low pass network filter 70 corresponds to the low pass network filter 24 of Fig. 1. The low pass network filter 70 passes the incoming signal to a receiver gate 76 which selectively passes the signal to a receiver 84.The differential output amplifier 53 performs the functions of isolating the signal from a transmitter 85 from conductors 44 and 45, and maintaining a balanced line condition on conductors 44 and 45, and therefrom on terminals 11 and 12, as is required to conform to the promulgated telephone communication standards. The input to the differential output amplifier 53 is connected to the low pass network filter 70 via conductor 67.

The impedance/switch network 50 detects the engagement of a hook switch (external) via the hook switch connectors 61 and 62 which connect to the external telephone unit so as to provide indication of when the telephone is in use. Upon detection of hook switch engagement, the impedance/switch network 50 places an impedance across conductors 44 and 45 to create a current source path for the incoming signals, in compliance with the line wire system regulations, in order that a central system may be alerted to the presence of an active remote unit (telephone), provide the required dial tone, and perform the other necessary functions. The existing practice in telephone systems is to provide a current loop path of approximately 20 milliamps by placing an impedance of 600 ohms in shunt connection with the wire pair. The impedance component of the impedance/ switch network 50 may be created from passive or active electronic device components and as such may be reduced to integrated circuit form.

The regulator 51 provides a stable DC output which provides a source of DC power to other subcomponents within the circuit that require an independent power source to operate. The differential input amplifier 52, differential output amplifier 53, impedance/switch network 70, regulator 51, and steering means 43 perform the functions of the external connection circuit 21 of Fig. 1. The ringing circuit 21 of Fig. 1 may be combined with the external connection circuit 20 as a single functional module.

The low pass network filter 70 performs the function of band limiting and spurious frequency filtering so as to conform to the wire line carrier standards as promulgated by the FCC.

The low pass network filter 70 is connected to the receiver gate 76 via conductor 75, and to a transmitter gate 90 via conductor 79.

The receiver gate 76 is connected to the receiver 84 via conductor 82. The receiver gate 76 selectively passes the signal from the low pass network filter 70 to the receiver 84 in accordance with an enabling signal provided along conductor 80 from an oscillator switching circuit 81. The incoming signal is selectively passed through the receiver gate 76 via conductor 82 to a receiver connector 83 which allows for connection to the external receiver 84 in the telephone unit. The receiver 84 may be a speaker or any similar electronically activated transducer. The low pass network filter 70 may be an active or passive filter, and as such may be reduced to integrated circuit form.

An outgoing, transmitted, signal originates in an acoustic to electrical transducer, transmitter 85, of the microphone type, such as a carbon element microphone. The transmitter 85 is externally located within the telephone handset or otherwise contained in the remote unit. The transmitter 85 is connected to a transmitter connector 86 which in turn is connected to the transmitter gate 90 via conductor 87. The transmitter gate 90 selectively passes the signal from the transmitter 85 to the low pass network filter 70 via conductor 79 in response to an enabling signal from the oscillator switching circuit 81 conveyed via conductor 92 to the transmitter gate 90. The oscillator switching circuit 81 alternately and exclusively enables either the receiver gate 76 or the transmitter gate 90 so as to allow only one of these gates to be enabled at any point in time.The low pass network filter 70 is connected to the differential output amplifier 53 which is connected to the conductors 44 and 45, connecting therefrom back to the external wire pair via terminals 11 and 1 2.

The outgoing signal passes via the low pass network filter 70, where high frequency spurious signals resulting from the high speed commutation of the receiver gate 76 and the transmitter gate 90 in response to the enabling signals from the oscillator switching circuit 81 are cancelled as a result of the filter action, but without affecting the transmitted or received signals. The filtered signal is conducted from the low pass network filter 70 via conductors 66 and 67 to the differential output amplifier 53 which is connected to the steering means 43. The filtered outgoing signals are then passed from the steering means 43 to the terminals 11 and 1 2 which provide for connection to the external wire pair of the central office switching system.The option exists to connect a dialing encoder 93 signal via conductor 91 to the summing input of the differential output amplifier 53 so as to provide a medium for connecting any frequency type dialing means to the external wire pair without distrubing the balanced line conditions necessary to comply with the appropriate regulations. The dialing encoder 93 may either be a self-actuated /self-contained dialing system or connect via dialing connector 94 to an external activation means 95 such as a push button keyboard pad or binary computer output.

Referring to Fig. 3, one embodiment for providing the desired isolation and maintaining a balanced line condition with the hybrid digital hybrid from Fig. 2 is illustrated. The terminals 11 and 1 2 which provide for connection to the external central system line pair, are connected to a primary winding 100 of a transformer 101 which provides the necessary isolation and line balancing functions to comply with the communications standards. A switch 109 is also connected to terminal 11 for providing on-line connection of the remote unit 10 to the central system.

The secondary winding 102 of the transformer 101 is connected to a low pass network filter 1 03. The low pass network filter 103, performing the functions as described with reference to Fig. 2, is connected to the sending circuit 104 and the receiving circuit 105 via conductors 106 and 107 from which point the circuit operates as described with reference to Fig. 1 above.

Referring now to Fig. 4, there is shown a block diagram of the digital hybrid structure contained within the electronic telephone 10 as shown in Fig. 2. Terminals 11 and 12 are connected to an external connection circuit 11 0. The external connection means 110 is connected to a low pass network filter 111 via connectors 11 2 and 11 3. The low pass network filter 111 is connected to a transmitter gate 11 4 via conductor 11 5 and to the receiver gate 11 6 via conductor 11 7. The receiver gate 11 6 is selectively biased so as to permit the incoming signal to pass to a receiver 1 20 via conductor 1 21. The receiver gate 11 6 is enabled to pass the incoming signal to the receiver 1 20 in response to an enabling bias signal from a second voltage divider 1 22 connected via conductor 1 21.

The second voltage divider means 1 22 provides the enabling bias signal to the receiving gate 11 6 in response to a gating signal from a receiving switch 1 23 connected to the second voltage divider means 1 22 via conductor 1 24. The receiving switch 1 23 is periodically activated by a receiver clock signal from an oscillator 125 connected by conductor 126.

Second voltage divider means 1 22 is provided with a bias reference voltage from a DC power source 1 27 via conductor 1 28.

The transmitter gate 11 4 selectively passes signals from a transmitter 130, connected by conductor 1 31 to the transmitter gate 114, in response to the enabling bias signal from a first voltage divider 1 32 which is also con nected via conductor 1 31 to the transmitter gate 114.The DC power source 127 provides a reference bias level to a first voltage divider 132 as connected by conductor 1 33. The first voltage divider 1 32 provides the enabling bias signal to the transmitter gate 114 in response to a gating signal from a transmitting switch 1 34 which is connected to the first voltage divider 132 with conductor 1 35. The trans mitting switch 1 34 provides the gating signal to the first voltage divider 1 32 in response to a transmitting clock signal from the oscillator '1 25 which is connected to the transmitting switch 1 34 with conductor 1 36. The trans mitting clock signal from the oscillator 1 25 is a periodic signal which alternately enables, then disables the transmitting switch 1 34.

The oscillator 1 25 also provides a receiving clock signal, which is also a periodic signal, that alternately enables, then disables, the receiving switch 1 23. However, the receiving clock signal and the transmitting clock signal are exclusive and inverse signals, such that only one of these signals may be active at any time. Said another way, the transmitting switch 1 34 and the receiving switch 1 23 are never enabled simultaneously, but are enabled in an exclusive manner whereby only one is enabled at any given point in time.The net result of this automatic switching operation is to time share the external wire pair by alter nately connecting the receiver or the transmit ter in an exlusive and periodic manner, with out the adverse effects of connecting both the receiver and transmitter to the external wire pair simultaneously. The oscillator 1 25 oper ates at a gating frequency faster than the human ear can detect, alternately enabling the connection of increments of signals from the transmitter 1 30 and to the receiver 1 20 via the external connection means 110 to the terminals 11 and 1 2. An oscillator frequency of 2 to 2 1/2 times the upper frequency value of communications is sufficient to provide nondetectable reconstruction of the origi nal signals.In a preferred embodiment, an oscillator means 1 25 provides a gating frequency in the range of 22 to 25 kilohertz. An frequency between 20 and 200 kilohertz is adequate. However, filtering considerations enter into the precise decision.

The first voltage divider means 1 32 and second voltage divider means 1 22 may be implemented as passive or active electronic components.

Referring now to Fig. 5, a preferred embodiment in partial schematic/partial block diagram form of the digital hybrid of Fig. 4 is shown. The receiver gate 11 6 may be implemented as a diode 140. Similarly, the transmitter gate 114 may be implemented as a diode 141. The first voltage divider 132 may be implemented as a resistive element having two subelements 143 and 144 having a connection point 145 therebetween. Similarly, the second voltage divider 1 22 may be implemented in the form of a resistive element having two subelements 146 and 147 with a connection point 148 therebetween. Transmitting switch 1 34 may be implemented as a transistor 150, shown in Fig. 5 as an NPN transistor.A collector 1 51 of transistor 150 is connected to the connection point 1 45 of the first voltage divider 132, while a base 1 52 of transistor 1 50 is connected to the oscillator 1 25 through conductor 1 36. Similarly, the receiving switch 1 23 may be implemented as a transistor 1 60 from which a collector 1 61 is connected to the connection point 1 48 of the second voltage divider 122, and a base 162 is connected to the oscillator 1 25 via conductor 126.Resistive subelement 144 is connected to the DC power source 127, while resistive subelement 143 is connected to the cathode of the diode 141 as well as to the transmitter 1 30. Similarly the resistive subelement 146 is connected to the DC power source 127, and resistive subelement 147 is connected to the cathode of diode 140 as well as to the receiver 1 20. In operation, the oscillator 1 25 provides a receiver clock signal along conductor 1 26 and a transmitter clock signal along conductor 1 36 which are inverse and exclusive as discusssed above, and which alternate between a ground reference voltage and a second voltage, the second voltage being sufficient to bias the transmitter switch transistor 1 50 or the receiving switch transistor 1 60 into a saturating conducting state. As the transmitting switch 1 34 and the receiving switch 1 23 operate in an identical manner, the following discussion of the transmitting switch 1 34 is equally applicable to the receiving switch 123.The transmitting switch 1 34 is enabled or gated when the oscillator 1 25 provides the second voltage level so as to bias on transmitting switch transistor 1 50 which effectively grounds the first voltage divider 1 32 connection point 145, which further effectively grounds the cathode of diode 141 so as to bias diode 141 to an ON condition to allow passage of the transmitted signal emanating from transmitter 1 30. Simultaneously, the oscillator 1 25 has provided a reciever clock signal at the ground reference voltage potential so as to prevent receiving switch transistor 1 60 from conducting, thereby not affecting the potential at connection point 1 48 of the second voltage divider 122, and thus allowing the potential provided by the DC power source 1 27 to propagate through the second voltage divider 1 22 to the cathode of the receive gate diode 140. This potential is sufficient to back bias diode 1 40 so as to prevent signal propagation therethrough, and thus prevent the gated transmitted signal from feeding back to the receiver. During the subsequent clock cycle of the oscillator 125, the receiver clock signal is at the second bias voltage level, while the transmitter clock sig nal is at the ground reference potential, thereby gating the incoming signal to the receiver and inhibiting the output of the trans mitted signal in the manner as discussed above.

Referring to Fig. 6A, an alternate embodi ment of the receiver gate 11 6 and the trans mitter gate 114 of Fig. 5 is shown, in the form of bipolar transistors 1 70 and 171, respectively, connected as diodes, that is each transistor having its collector shorted to its base.

Referring to Fig. 6B, an alternate embodi ment of the receiver gate 11 6 and transmitter gate 114 of Fig. 5 is shown in the form of field effect transistors (FET) 1 72 and 173, respectively, connected as diodes, that is each transistor having its source shorted to its gate.

Referring to Fig. 6C, an alternate embodi ment of the first voltage divider 1 32 and second voltage divider 1 22 of Fig. 4 is shown in partial schematic/partial block diagram form, wherein the voltage divider is comprised of active element subparts. First voltage divider 1 32 has a first transistor 1 74 connected to the transmitter gate 114 and the transmitter 130 via drain 180.A source 1 81 of transistor 1 74 is connected to the common connection point 1 78 of the first voltage divider 1 32 and also is connected to a drain 1 82 of a second FET transistor 1 75. A source 1 83 of transistor 1 75 is connected to the power means 1 27. Similarly, a second voltage divider 1 22 has a first transistor 1 77 which has a drain 1 84 connected to the receiver gate 11 6 and the receiver 1 20. A source 185 of transistor 1 77 connects to the second voltage divider 1 22 interconnection point 1 79 as well as connecting to a drain 186 of transistor 1 76. A source 1 87 of transistor 1 76 connects to the power source 127. Transistors 174, 175, 176 and 177 are configured with each having its respective gate connected to its respective source.The first voltage divider 1 32 and second voltage divider 1 22 as described with reference to Fig. 6C operate in a manner similar to and compatible with the embodiments of first voltage divider 1 32 and second voltage divider 1 22 as described with reference to Fig. 5.

Referring now to Fig. 7, an alternate embodiment of the digital hybrid as shown in Fig. 4 is set forth in block diagram form.

Distinguishing Fig. 7 from Fig. 4, it is seen that the transmitting switch 1 34 and receiving switch 1 23 are functionally replaced by a complementary output flip flop 1 90. In operation, the oscillator 1 25 provides a clock signal output to the input of the complementary output flip flop 1 90. This clock signal toggles the complementary output flip flop between its two stable states. The outputs from flip flop 1 90 are complementary (i.e. inverse functions) and thus provide the mutual exclusivity required to maintain feedback isolation between the receiver 1 20 and transmitter 1 30.

A non-inverting output is connected to the first voltage divider means 1 32 via conductor 193, while an inverting output from the com plementary output flip flop 1 91 is connected to the second voltage divider means 1 22 via conductor 1 95. The resulting operation is as described above with reference to Figs. 5, and 6.

Referring now to Fig. 8, a schematic of a preferred embodiment of the impedance/ switch network 50 of Fig. 2 is shown. In operation, an activation signal is presented to hook switch connectors 200 and 201, con nector 201 passing the activation signal to the hook switch transistor gate 202, thereby activating hook switch transistor 203 into a conductive state. The current loop impedance 204 is thereby placed in shunt connection the the external line wire pair via terminals 11 and 12, thereby providing a current source path impedance in compliance to the require ment of the telephone system. Hook switch connectors 200 and 201 may also function as the input connectors for an external rotary dial or other pulsed means.

The electronic telephone 10 may be in an integrated circuit or discrete circuit form. The digital hybrid as disclosed herein obviates the need for transformers, and thereby allows its reduction to integrated circuit form using suitable techniques. As the entire electronic telephone may be constructed without transformers, circuit functions described herein are reducible to integrated circuit form, either discretely or as a single chip integrated circuit complete system. It will be understood, therefore, that the present invention contemplates the integration of all telephone circuit functions, as disclosed herein, in a monolithic integrated circuit structure.

Fabrication and design techniques necessary to implement these functions are well known in the art, and as such, are not discussed further herein. Although the invention has been described in part by making detailed reference to certain specific embodiments, such detail is intended to be, and will be understood to be, instructive rather than restrictive. It will be appreciated by those in the art that many variations may be made in the structure and circuits without departing from the spirit and scope of the invention.

Claims (20)

1. An electronic telephone comprising: external connection means for maintaining a balanced load and providing isolation interconnection to an external line pair medium connection; a transmitter; a receiver; and digital hybrid means operably connected to the external connection means, to the transmitter, and to the receiver, alternately ena bling increments of the transmitted and received electrical signals in a shared fashion at a frequency faster than the human ear can detect along a single pair of conductors, while limiting feedback between the receiver and the transmitter.

2. An electronic telephone as recited in Claim 1 wherein the digital hybrid means comprises: network filter means operably connected to the external connection means for cancelling high frequency signal components from the transmitted signal; gating means operably connected to the network filter means for selectively passing signals from the transmitter to the network filter means; gating means operably connected to the network filter means for selectively receiving signals from the network filter means and conducting the received signals to the receiver; and automatic switching means, oscillating at a gate frequency faster than the human ear can detect, operably connected to the receiver gating means and to the transmitter gating means, which alternately selects the receiver gating means or the transmitter gating means so as to alternately enable increments of signals from each, respectively, to connect to the network filter means.

3. An electronic telephone as recited in Claim 1 which is an integrated circuit.

4. An electronic telephone as recited in Claim 2 which is an integrated circuit.

5. An electronic telephone as recited in Claim 1 or Claim 2 wherein the external connection means includes a transformer for connection to the external line pair to provide isolation.

6. An electronic telephone as recited in Claim 1 or Claim 2 wherein the external connection means comprises: steering means for connection to the external medium connection which converts alternating signals from the external medium connection into polarized signals; ringing filter means connected to the steering means and selectively passing signals within or below a first frequency range; a ringer operably connected to the ringing filter means; an impedance/switch network for providing a current loop source to the external connection medium upon receipt of an active status signal; receiver amplifier means, having differential inputs, to provide balanced laoding, connected to the digital hybrid means, and having a provisional input for connection of an externally provided input; and transmitter amplifier means having differential outputs to provide balanced loading, connected to the digital hybrid means, and having a provisional input for connection of an externally provided input signal.

7. An electronic telephone as in Claim 6 further including a telephone keyboard to the provisional input of the receiver amplifier means.

8. An electronic telephone as in Claim 6 wherein the externally provided input is a digitally encoded signal.

9. An electronic telephone as in Claim 6, further including: regulator means connected to the external connection means for converting an incoming AC signal source to a constant DC power source.

10. An electronic telephone as recited in Claim 6 which is a one chip integrated circuit.

11. A digital hybrid coupler comprising: network filter means, operably connected to an external connection means, for cancelling high frequency signal components; gating means, operably connected to the network filter means, for selectively passing signals from a transmitter to the network filter means; gating means, operably connected to the network filter means, for selectively passing signals from the network filter means to a receiver; and automatic switching means, oscillating at a gate frequency faster than the human ear can detect, operably connected to the receiver gating means and to the transmitter gating means, which alternately selects the receiver gating means or the transmitter gating means so as to alternately enable increments of signals from each, respectively, to connect to the network filter means, thereby affectuating non-detectible reconstruction of the signals from each.

1 2. A digital hybrid coupler as recited in Claim 11 which is an integrated circuit.

1 3. A digital hybrid coupler as recited in Claim 11 wherein the transmitter gating means comprises: a transmitter gate, operably connected to the network filter means and to the transmitter, for selectively passing a signal from the transmitter to the network filter means; a voltage divider, operably connected to the transmitter gate and to a reference power source, which selectively connects a reference power source signal to the transmitter gate; and a transmitting switch, operably connected to the transmitter voltage divider and to the automatic switching means, which in response to a gating clock from the automatic switching means disables the transmitter voltage divider from passing the reference power source signal to the transmitter gate, thereby disabling the transmitter gate from passing the signal from the transmitter to the network filter means.

1 4. A digital hybrid coupler as recited in Claim 11 wherein the receiver gating means comprises: a receiver gate, operably connected to the network filter means and to the receiver, which selectively passes signals from the receiver to the network filter means; a receiver voltage divider, operbly connected to the receiver gate and to the reference power source, which selectively passes a reference power source signal to the receiver gate so as to enable the receiver gate to pass the signal from the receiver to the network filter means; and a receiving switch, operably connected to the receiver voltage divider and to the automatic switching means, which in response to a gating clock signal from the automatic switching means disables the receiver voltage divider from passing the reference power source signal to the receiver gate and thereby provents passage of the signal from the receiver to the network filter means.

1 5. A digital hybrid coupler as recited in Claim 11 wherein the automatic switching means is an oscillator.

1 6. A digital hybrid coupler as recited in Claim 1 3 wherein the transmitter gate is a bipolar P-N junction.

1 7. A digital hybrid coupler as recited in Claim 1 3 wherein the transmitting switch is a transistor.

1 8. A digital hybrid coupler as recited in Claim 14 wherein the receiver gate is a bipolar P-N junction.

19. A digital hybrid coupler as recited in Claim 1 4 wherein the receiving switch is a transistor.

20. A digital hybrid coupler as recited in Claim 11 wherein the receiver gating means and transmitter gating means comprise: a complementary output flip flop, connected to the automatic switching means, which in response to a gating clock signal toggles the complimentary outputs between two reference potential levels representing binary states, of an enabling potential and a disabling potential; a receiver voltage divider, operably connected to one of the complementary outputs of the flip flop, further connected to a reference power source signal;; a receiver gate, operably connected to the receiver voltage divider and further connected to the receiver, which passes a signal from the receiver to the network filter means in response to the passage of the reference power source signal by the receiver voltage divider in response to the enabling potential reference of the one output of the complementary output flip flop; a transmitter voltage divider, operably connected to the other output of the complementary output flip flop and further connected to the reference potential source signal; and a transmitter gate, operably connected to the transmitter voltage divider, the network filter means, and the transmitter, the transmit ter gate selectively passing a signal from the transmitter to the network filter means in response to the reference potential source signal passage by the transmitter voltage divider, the transmitter voltage divider passing the reference potential source signal in response to the enabling reference potential provided by the other output of the complementary output flip flop, the one output and the other output of the complementary output flip flop being inverse signals such that when the one output of the complementary output flip flop is at the enabling reference potential, then the other output of the complementary flip flop is at the disabling reference potential, and vice versa.