GB2030810A

GB2030810A - Integated injection logic circuit

Info

Publication number: GB2030810A
Application number: GB7929516A
Authority: GB
Original assignee: Philips Gloeilampenfabrieken NV
Current assignee: Koninklijke Philips NV
Priority date: 1978-08-28
Filing date: 1979-08-24
Publication date: 1980-04-10
Also published as: FR2435085A1; JPS5531400A; IT7925281A0; DE2837476A1; GB2030810B; ES483621A1; IT1122820B

Abstract

In a combination of an integrated injection logic circuit (T1, T2, T10) and a current source circuit (V) connected to the injectors of the logic circuit for energising them, the collector currents and hence the speeds of the logic circuit inverter transistors are standardised from batch to batch of such combinations by comparing the collector current (ICT2) of an otherwise non- controlled transistor (T2) of the integrated circuit, which transistor is itself provided with a current injector (T1), with the output current (Iref) of a reference current source and controlling the output current of the current source circuit (V) in such manner as to reduce any deviation of the difference from a predetermined value to zero. <IMAGE>

Description

SPECIFICATION Integrated injection logic circuit with injector-energising current source The invention relates to a combination of an integrated injection logic circuit comprising a plurality of transistor/current injector structures, and a current source circuit connected to the injectors of said structures for energising said injectors.

An integrated injection logic circuit is known, for example from the article Integri- erte Injektiorslogik, ein neuartiges Prinzip für Digitalschaltungen" in Valvo-Berichte, Band XVIII, Heft 1/2, pages 215 to 226.

Fig. 1 of the accompanying drawings shows a schematic cross-section through part of a possible such integrated injection logic circuit, and Fig. 2 of said drawings shows the corresponding circuit diagram. The part of the injection logic circuit shown comprises a lateral PNP-transistor T1, which constitutes a bias current injector, and an inversely operated vertical NPN-transistor T2 which is supplied with forward bias current by the injector.

Fig. 1 therefore shows a transistor/current injector structure. Further vertical NPN transistors may be supplied by the injector T1 if desired. The injector T1 is supplied with an energising current 15. As a result of the lateral transistor action between the zones 1, 2 and 3 in Fig. 1 a current 15 flows into the base 3 of the transistor T2.

Owing to the fact that the structure T2 is operated in the inverse manner the collector of the NPN transistor T2 may take form of a multiple collector, so that several structures T1, T2 may be coupled together in a simple manner to form logic circuits. When this is done the various transistors T2 operate as inverters in known manner. The injector current I required for such a logic circuit is the sum of the individual injector currents Is if the emitter-base junctions of the various injectors are connected in parallel. This current is conventionally fed to such an injection logic circuit from a fixed constant current source.

However, in circuits which are thus energised the collector currents and the switching speeds of the inverters are liable to vary substantially from one such integrated circuit to another, these variations resulting from tolerances in the current gain(s) of the PNPinjector(s) T1 (approx. 2 to 20) and in the current gain(s) of the NPN-inverter transistor(s) T2 (approx. 4 to 20). Each collector of an inverter should be capable of taking over the base current of one other inverter. If all inverters receive equal base currents from the corresponding injector(s), the numerical value of the current gain of each individual inverter must not be smaller than the number of its collectors. The current dependence of the current gain of a transistor thus demands a minimum collector current of an inverter.

It is an object of the invention to provide a combination of the type mentioned in the preamble which is such that the inverter collector current levels of the integrated injection logic circuit can be maintained substantially constant from one such integrated circuit to another.

The invention provides a combination of an integrated injection logic circuit comprising a plurality of transistor/current injector structures, and a current source circuit connected to the injectors of said structures for energising said injectors, characterised in that a collector of at least one transistor of a said structure and the output of a reference current source are coupled to a control input of said current souce circuit in such manner that any deviation of the difference between the current carried by said collector(s), or a current representative thereof, and the output current of said reference current source from a given value will result in control of the output current of said current source circuit in a sense such as to reduce said deviation. Said given value may be zero or finite.

Such a combination enables the collector currents of the various inverter transistors, and hence their speeds, to be given the values required regardless of manufacturing tolerances which result in deviations of the current gains of the transistor/current injector structures. It also makes it possible to energize analog circuit elements from the collector of the transistor of a transistor/current injector structure in a comparatively accurate manner, if required.

Some embodiments of the invention will now be described, by way of example with reference to the accompanying diagrammatic drawings. In the drawings Figure 1 shows the aforesaid cross-section through part of an integrated injection logic circuit which accords with the present state-ofthe-art, Figure 2 shows the aforesaid circuit diagram corresponding to the arrangement of Fig. 1, Figure 3 shows the circuit diagram of a first embodiment of the invention, Figure 4 shows a possible modification of the embodiment of Fig. 3, Figure 5 shows another possible modification of the embodiment of Fig. 3, and Figure 6 shows the circuit diagram of a second embodiment of the invention.

In Fig. 3 the injectors of an integrated injection logic circuit shown within dashed lines and comprising a transistor/current injector structure T1, T2 and further transistor/ current injector structures the injector(s) of which is (are) denoted by a diode T10 are supplied with energising current I the value of which is determined by the output of an amplifier V.The resulting collector current 1CT2 of the transistor T2 (the base of which is connected only to the output of the injector T1) is compared with a reference current Iref and, in response thereto, the amplifier V controls the total injector current I injected into the integrated injection logic circuit in such a way that 1CT2 is made equal to Ires, at the same time bringing the collector currents of the other transistors to the required value(s).

As an alternative the transistor T2 which forms part of the transistor/current injector structure T1, T2 may be connected as a current mirror as shown at T21 in Fig. 4.

It is also possible to generate the current which is compared with the output of the reference current source by means of a conventional current mirror circuit arrangement which merely mirrors the injector current. One possible such arrangement is constituted by conventional transistors T1 and T22 in Fig. 5, which replace the transistor/current injector structure T1, T21 of Fig. 4. T1 1 symbolically represents a further injection logic circuit the or each injector of which is connected in known manner in series with the or each injector of the first injection logic circuit T10.

The embodiment of Fig. 6 comprises a reference current source, constituted by the transistors T30 to T35, a control loop formed by the transistors T36 to T43, and the injection logic circuit to be energized, which includes the transistor/current injector structures: T40, T41 and T42, T43 and T45, T44 as well as further transistor/current injector structures the injectors of some of which are shown collectively at T47 and the injectors of others of which are shown collectively at T48.

The arrangement also includes analog circuits denoted by blocks A and B respectively.

The reference current 1ref supplied by the reference current source is compared with the sum of the collector currents of the transistors T40 and T43 which operate as "measuring transistors". Two measuring transistors are employed, which may be arranged remote from each other on the chip accommodating the injection logic circuit so as to improve the compensation for tolerances obtained. The reference current and the said sum are compared with each other on the junction K (which also constitutes the control input of a current source circuit constituted by the transistors T36 and T37). If the difference deviates from a given finite value the total injector energising current Ij is controlled via T36 and T37 to reduce this deviation to substantially zero. A resistor R1 serves to limit the sum of the collector currents of T36 and T37 in the event of defects.

The two injection logic sections the injectors of which are represented by T47 and T48 respectively are connected in series as far as their injectors are concerned in order to make more effective use of the available current. It will be obvious that the measuring transistors may alternatively be arranged in the second or a further injection logic section.

The transistors T38 and T39, which are connected as diodes provide the voltage offsets required; if the measuring transistors are arranged in another injection logic section or level as previously mentioned further such diodes will be required in conformity with the number of sections between this other section and the point K.

The analog circuit A derives its bias currents 1A from the injection logic circuit via the transistor T45.

The analog circuit B, which is coupled to the reference current source via a transistor T49, has its supply current path connected in series with the injector energising current path through the injection logic circuit, so that its current consumption contributes to the injector energising current It will be evident that, instead of comparing the actual collector current(s) of the measuring transistor(s) with the output of the reference current source a current which is merely representative of said collector current(s) may be compared therewith. Such a current may be derived from the collector current(s) by means of a current mirror circuit (which need not necessarily produce a ratio fl :1 between its input and output currents).

Claims

1. A combination of an integrated injection logic circuit comprising a plurality of transistor/current injector structures, and a current source circuit connected to the injectors of said structures for energising said injectors, characterised in that a collector of at least one transistor of a said structure and the output of a reference current source are coupled to a control input of said current source circuit in such manner that any deviation of the difference between the current carried by said collector(s), or a current representative thereof, and the output current of said reference current source from a given value will result in control of the output current of said current source circuit in a sense such as to reduce said deviation.

2. A combination as claimed in Claim 1, characterised in that a said transistor has a second collector which is connected to the base of that transistor.

3. A combination as claimed in Claim 1 or Claim 2, characterised in that the current source comprises a current amplifier to which the collector(s) specified in Claim 1 and the output of the reference current source are connected.

4. A combination of an integrated injection logic circuit comprising a plurality of transistor/current injector structures, and a current source circuit connected to the injectors of said structures for energising said injectors, substantially as described herein with reference to Figs. 3, 4, or 6 of the drawings.