GB2027992A - Improvements in or relating to MOS field effect transistors for high voltage use - Google Patents
Improvements in or relating to MOS field effect transistors for high voltage use Download PDFInfo
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- GB2027992A GB2027992A GB7927555A GB7927555A GB2027992A GB 2027992 A GB2027992 A GB 2027992A GB 7927555 A GB7927555 A GB 7927555A GB 7927555 A GB7927555 A GB 7927555A GB 2027992 A GB2027992 A GB 2027992A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
- H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
- H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
- H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
In an MOS field effect transistor in addition to doped semiconductor zones forming the source (4) and drain (5) zones, there is provided at least one further semiconductor zone (5, 6) preferably ion implanted and directly linked to the source and/or drain zone e.g. formed by diffusion, and of the same doping type, the or each further zone (5, 6) extending into the interior of the semiconductor in the direction of the gate. The or each further semi conductor zone (5, 6) is spaced by a distance d from the semiconductor surface (7) in which the source and drain zones are formed, a gate (12) being arranged on an insulating layer (11) on said surface (7) in such manner that there is an offset distance LA between the outer boundary of the gate (12) and the adjacent boundary of the source or drain zone, at the semiconductor surface. The source and drain zones can be arranged either symmetrically or asymmetrically with respect to the gate. <IMAGE>
Description
SPECIFICATION
Improvements in or relating to MOS field effect transistors for high voltage use
The present invention relates to MOS field effect transistors for high voltage use. Field effect transistors can generally be operated with supply voltages of up to about 30 V. When supply voltages which are higher than 30 V are connected, at the drain end of the channel increases in the electric field occur at the boundary between the semiconductor substrate and the gate insulating layer, for example, between silicon and silicon dioxide, which leads to breakdown occurring primarily at this point. Measures designed to increase the dielectric strength serve to reduce this increase in field.By using ion-implanted zones at the drain end, stepped gate insulating layers, and field plates, it is possible to produce MOS field effect transistors having a dielectric strength which is greater than 30 V.
The invention relates in particularto MOS field effect transistors having two doped semiconductor zones of one conductivity type which extend from the surface of a semiconductor substrate into its interior, and form the source and drain zones, these zones being separated from one another by a semiconductor region of the opposite conductivity type, the surface of the semiconductor substrate located between the source and drain zones being covered by an electrically insulating layer which also covers parts of the source and drain zones, and in which from at least one of the source and drain zones, a further semiconductor zone immediately adjacent to the source or drain zone and also of the one conductivity type extends into the semiconductor substrate in the direction of the gate.
From an address entitled "A high BVDS MOSFET by ION implantation", given by K. Tokuyama, T.
Yoshino and Y. Iga, on the occasion of the Micro
Electronic Congress of 1976, it is known to increase the dielectric strength of MOS field effect transistors from 30 V by about 50 V to a maximum of 80 V. It is stated that an effective increase in the dielectric strength of a MOS transistor can be achieved by ion implantation between a strongly doped drain zone and those parts of the semiconductor surface which face the gate. Although doped semiconductor zones which extend along the semiconductor surface into regions within the drain zone are shown, it is also shown that those ion-implanted sub-zones which extend into the semiconductor within the drain zone do not contribute to an effective increase in the dielectric strength of a field effect transistor of this kind.The total increase in the dielectric strength of a
MOS field effect transistor is much more to be ascribed to the ion implantation and thus weaker doping of a zone which is close to the semiconductor surface and to the gate outside the drain zone.
In a paper entitled "High Voltage DSA-MOS Transistorfor Electroluminescent Display", by Katsuno
bu Awane, Katsumasa Fujii, Toshiaki Yamano,
Hiroshi Tamaki, Tetsuo Biwa, Hironori Hattori and
Takeo Fujimoto, presented in February 1978 on the occasion of the IEEE International Solid-State Circuits Conference, MOS field effect transistors having a high breakdown voltage were disclosed which comprise ion-implanted zones which extend from the semiconductor surface into the interior, and also stepped gate oxide layers and field plates, so that very high breakdown voltages between the source and drain can be achieved. However, the MOS field effect transistors described in this paper are arranged asymmetrically as regards the source and drain.In many cases, e.g. when MOS field effect transistors are to be used as transfer gates, transistors with such asymmetry are useless, and it is therefore desirable to be able to achieve a high dielectric strength in MOS field effect transistors which are symmetrical in respect of their source and drain zones.
It is therefore an object of the present invention to provide an MOS-field effect transistor having a high breakdown voltage and in which in addition the arrangement of the source and drain zones can be either symmetrical or asymmetrical as desired.
According to the invention, there is provided an
MOS field effect transistor comprising two doped semiconductor zones of one conductivity type extending from a surface of a semiconductor body and forming the source and drain zones of the transistor, said zones being separated by a part of said body of the opposite conductivity type constituting the channel of said transistor, an electrically insulating layer on said surface overlying said channel zone and also covering a part of each of said source and drain zones, a gate arranged on said insulating layer above said channel zone in such manner that at least one of the edges of the gate adjacent to the source and drain zones respectively is spaced from the boundary of the respective one of said source and drain zones, and at least one of said source and drain zones being provided with a further semiconductor zone of said one conductivity type contiguous therewith and extending from said source or drain zone into the interior of said body in the direction towards said gate, the or each said further zone being spaced from said surface of the semiconductor body.
MOS field effect transistors in accordance with the invention have the advantage that they have a high di-electric strength of 200 V or more, and also allow either spatially symmetrical or asymmetrical transistor arrangements as regards the source and drain zones, to be obtained. It is therefore possible to use these high-voltage-resistant MOS field effect transistors in transfer gates.
It is advantageous if the or each further semiconductor zone extends parallel to the surface of the semiconductor substrate in which the source and drain zones are formed.
It is also advantageous if the further semiconductor zones are produced by ion implantation. This has the advantage that the further semiconductor zones can be produced technically easily so as to lie at a given distance from the semiconductor surface. The depth of the implantation zones in the semiconductor substrate can be adjusted accordingly by varying the implantation energy of the implanted ions:
It is particularly advantageous if the average penetration depth of the ions is from 0.Sum to 2jim, in particular, 1 jim, these values having been found to be particularly favourable as regards high breakdown voltage for conventional MOS field effect transistors.
In many cases, e.g. for the production of transfer gates, it is advantageous if the source and drain zones of the transistor are symmetrically arranged.
In some case, it is also advantageous for the transistor to be formed in a semiconductor body which simultaneously serves as a carrier. MOS field effect transistors of this kind can, for example, be used with advantage in integrated circuits for connecting high voltages of alternating polarity.
For the production of certain MOS field effect transistors it is advantageous for the MOS transistor to be arranged on a carrier made of insulating material, e.g. sapphire or spinel. MOS field effect transistors constructed in this way can also be used, for example, in integrated circuits, for high voltage applications.
The semiconductor substrate material used is preferably silicon.
An advantageous process for producing MOS field effect transistors in accordance with the invention comprises the steps of:
(a) producing semiconductor zones to form the source and drain zones of the transistor by diffusion from the surface of a semiconductor body using a suitable mask;
(b) applying to the surface a gate insulator layer, e.g. of SiO2;
(c) applying the gate of the transistor to the gate insulation; and
(d) producing the further semiconductor zone or zones by ion implantation, the applied gate and thicker insulating layers serving as an implantation mask.
This production process has the advantage that the deep lying implanted parts of the source and drain zones are self-aligned relative to the gate, and under certain circumstances, it is possible to avoid using a mask. This process is used to produce MOS circuits, in particular for high voltage uses.
An alternative process for the production of MOS field effect transistors according to the invention comprises the steps of:
(a) producing semiconductor zones serving as the source and drain zones by diffusion from the surface of a semiconductor body using a suitable mask;
(b) providing the surface of the semiconductor body with a thin insulating layer, for example, by oxidation;
(c) forming said further zones by ion implantation using a photo-lacquer mask produced photolithographically; and
(d) after removal of the lacquer mask, applying the gate and applying thicker insulating layers, e.g.
semiconductor oxide layers, to required parts of the transistor surface.
The two processes described above can similarly be used if an insulating substrate, consisting, for example, of sapphire or spinel, is used in place of a silicon substrate. MOS field effect transistors so produced have the advantage that they are dielectrically insulated from one another. Such MOS field effect transistors can be used in integrated circuits for high voltages.
The invention will now be further described with reference to the drawing, in which Figures 1, 2 and 3 are similar schematic side sectional views of three different forms of MOSFET, according to the invention.
Figure 1 shows a symmetrically arranged MOS field effect transistor 1 formed in a semiconductor substrate, with an offset gate, and ion-implanted further zones. A drain zone 3 and a source zone 4 in the form of p±doped are produced by diffusion in a n-doped silicon substrate 2. Parallel to the surface 7 of the substrate 2 and spaced at a distance d therefrom, narrow ion-implanted further semiconductor zones 5 and 6 extend from the drain zone 3 and the source zone 4 respectively into the substrate in the direction of the gate. The implanted semiconductor zones 5, 6 are p-doped. These zones extend from the drain boundary 8 or the source boundary 9 as the case may be into the semiconductor interior through a distance LB The two implantation zones 5 and 6 are separated from one another by a distance 1.A gate insulator layer 11, consisting, for example, of a silicon oxide or silicon nitride, is arranged on the semiconductor surface 7 in such a way that it covers the area between the source zone 4 and the drain zone 3, and edge portions of these two zones. A gate 12 is arranged on the gate insulator 11 in such a way that a gap having a length LA when projected onto the surface 7 is in each case formed between the gate 12 and the drain zone 3 or source zone 4.
Figure 2 illustrates a symmetrically-arranged MOS field effect transistor 10 formed on an insulating substrate and having an offset gate, and ionimplanted further zones. A drain zone 3 and a source zone 4 consisting of p±doped silicon are formed in a semiconductor body arranged on an insulating substrate 13 consisting, for example, of sapphire.
From the drain zone 3 an implanted semiconductor zone 5 extends into the interior of the semiconductor body towards a gate 12, arranged on a gate insulator 11, the implanted semiconductor zone 5 being spaced by a distance dfrom the semiconductor surface 7. An implanted further zone 6 is arranged similarly starting from the source zone 4. On the semiconductor surface 7 there, the gate insulator 11 is arranged consisting, for example, of silicon oxide which covers the semiconductor surface 7 between source and drain in such a way that edge regions of the source 4 and drain 3 are also covered by the insulating layer. The gate 12 is arranged on the gate insulator layer 11 in such manner that it is spaced by a distance LA from both the source 4 and the drain 3.
A field effect transistor as illustrated in Figure 2 can be produced by epitaxially applying a semiconductor layer to an insulating substrate. This semiconductor layer may consist, for example, of ndoped silicon or undoped silicon into which an n-dopant is subsequently introduced. Then p±doped drain and source zones are formed and the gate insulating layer 11, consisting, for example, of a silicon oxide or silicon nitride, is applied to the semiconductor surface 7. The semiconductor material which lies outside the semiconductor zones on the substrate surface illustrated in Figure 2 is then removed by photo-etching (insular etching). The implanted further zones 5 and 6 are then produced and the gate 12 is applied on the gate insulator 11.
Figure 3 illustrates an asymmetrically-arranged
MOS field effect transistor 20 formed on an insulating substrate and having an offset gate, and one ion-implanted further zone 5. Apart from the asymmetry in respect of source and drain, the arrangement of Figure 3 corresponds to that of Figure 2 and corresponding parts have been provided with the same reference numerals. Figure 3 thus differs from
Figure 2 in respect of asymmetry with regard to source and drain, and by the fact that only one further ion-implanted zone 5 is provided adjacent to the drain zone 3. The further zone 5 and the source zone 4 are separated by a distance 1, zone 5 commencing from the drain zone 3 and leading into the semiconductor interior towards the gate has a length LB, and the edge of the gate 12 is spaced from the drain zone 3 by a distance LA.
The particulardopings of the individual semiconductor zones described with reference to Figures 1 to 3 is in no way essential. In fact, similar field effect transistors can be constructed in which the p-doped zones are replaced by n-doped zones and the n-doped zones are replaced by p-doped zones.
Just as Figure 3 represents an asymmetrical field effect transistor corresponding to the symmetrical field effect transistor of Figure 2, so it is also possible to construct an asymmetrical field effect transistor corresponding to Figure 1. This has not, however, been illustrated.
Metals, e.g. aluminium or molybdenum or polysilicon can be used as materials for the gates 12 in
Figures 1 to 3. Layers of a plurality of the aforementioned materials or alloys of the aforementioned metals can also be used for this purpose.
If the implanted further zones 5 and 6 were omitted, and the offset distance LA was sufficiently great, field effect transistors in accordance with
Figures 1 to 3 would not function since the current flow in the channel zone would not be ensured.
However, an adequate offset, in particular in the vicinity drain zone, is necessary, as previously mentioned, in order to reduce a field increase at the drain zone between the semiconductor surface 7 and the overlying gate insulator layer 11. The implanted semiconductor zones 5 and 6 arranged inside the semiconductor body do, on the one hand, bridge the channel zone enabling a channel current to flow, but, on the other hand, do not result in any considerable increase in the field at the drain-side boundary between the semiconductor surface 7 and the insulator layer 11. If, on the other hand, it is ensured that the distance 1 separating the implanted further zones 5 and 6 is sufficient to prevent a voltage breakdown at this point, the dielectric strength of
MOS field effect transistors can in this way be reduced.Moreover, in order to avoid breakdown, the distance d of the implanted further zones 5 and 6 from the semiconductor surface 7 should not be too small, nor, on the other hand, too great, in order to ensure a flow of current between the source and the drain. Experiments have shown that in MOS field effect transistors in accordance with the invention, the distance d is preferably greater than 0.51lem, and in particular is from 1 jim to 2jim. For example, when silicon oxide is used, the layer thickness of the gate insulator may be 100 to 200 nm. If a self-aiigning gate is used, i.e. if the gate itself is used as a mask during the ion implantation, the gate thickness must be matched to the desired penetration depth of the ions. With an average ion penetration depth of 1 jim, an aluminium gate must have a layer thickness of at least 1 jim.
With suitable dimensioning, a breakdown voltage of more than 200 V can be achieved with the MOS field effect transistors of the invention. MOS field effect transistors in accordance with the invention of symmetrical design can be used in transfer gate circuits and are characterised by a substantially higher dielectric strength than previously known symmetrical arrangements. Hitherto, correspondingly high dielectric strengths of MOS field effect transistors have only been known with asymmetrical arrangements, e.g. using stepped gate insulating layers.
Claims (14)
1. An MOS field effect transistor comprising two doped semiconductor zones of one conductivity type extending from a surface of a semiconductor body and forming the source and drain zones of the transistor, said zones being separated by a part of said body of the opposite conductivity type constituting the channel of said transistor, an electrically insulating layer on said surface overlying said channel zone and also covering a part of each of said source and drain zones, a gate arranged on said insulating layer above said channel zone in such manner that at least one of the edges of the gate adjacent to the source and drain zones respectively is spaced from the boundary of the respective one of said source and drain zones, and at least one of said source and drain zones being provided with a further semiconductor zone of said one conductivity type contiguous therewith and extending from said source or drain zone into the interior of said body in the direction towards said gate, the or each said further zone being spaced from said surface of the semiconductor body.
2. An MOS field effect transistor as claimed in
Claim 1, wherein the or each said further zone extends substantially parallel to the surface of said semiconductor body containing said source and drain zones.
3. An MOS field effect transistor as claimed in
Claim 1 or Claim 2, wherein the or each said further zone is produced by ion implantation.
4. An MOS field effect transistor as claimed in
Claim 3, wherein the average penetration depth of the ions used to form said further zone or zones is from 0.51lem to 2jim.
5. An MOS field effect transistor as claimed in
Claim 4 wherein said average ion penetration depth is 1 lim.
6. An MOS field effect transistor as claimed in any one of the preceding Claims wherein said source and drain zones are symmetrically arranged with respect to the gate.
7. An MOS field effect transistor as claimed in any one of the preceding Claims incorporated in a semiconductor body which simultaneously serves as a carrier.
8. An MOS field effect transistor as claimed in any one of Claims 1 to 7, arranged on a carrier made of insulating material.
9. An MOS field effect transistor as claimed in
Claim 8 wherein said carrier is made of sapphire or spinel.
10. An MOS field effect transistor as claimed in any one of the preceding Claims wherein said semiconductor body is of silicon.
11. An MOS field effect transistor substantially as hereinbefore described with reference to and as shown in any of Figures 1 to 3 of the drawing.
12. A process for the production of an MOS field effect transistor as claimed in Claim 1 comprising the steps of:
(a) producing in a semiconductor body zones to form the source zone and drain zone of the transistor by diffusion from a surface of the body using a suitable mask;
(b) applying a gate insulator layer to said surface;
(c) applying the gate of said transistor to said gate insulator layer; and
(d) producing said further semiconductor zone or zones by ion implantation using the applied gate and thicker insulating layers as an implantation mask.
13 A process for the production of an MOS field effect transistor as claimed in Claim 1 comprising the steps of:
(a) producing semiconductor zones serving as source and drain zones by diffusion from the surface of a semiconductor body using a suitable mask;
(b) providing said surface with a thin insulating layer;
(c) forming said further zone or zones by ion implantation using a photo-lacquer mask produced photolithographically; and
(d) after removal of the lacquer mask applying the gate and applying thicker insulating layers to required surfaces of said transistor.
14. A process as claimed in Claim 13 wherein in step (b) said thin oxidising layer is produced by oxidation.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19782834724 DE2834724A1 (en) | 1978-08-08 | 1978-08-08 | MOS FIELD EFFECT TRANSISTORS FOR HIGHER VOLTAGES |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2027992A true GB2027992A (en) | 1980-02-27 |
| GB2027992B GB2027992B (en) | 1982-10-06 |
Family
ID=6046501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7927555A Expired GB2027992B (en) | 1978-08-08 | 1979-08-07 | Field effect transistors for high voltage use |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5524497A (en) |
| DE (1) | DE2834724A1 (en) |
| FR (1) | FR2433240A1 (en) |
| GB (1) | GB2027992B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2150348A (en) * | 1983-11-29 | 1985-06-26 | Philips Electronic Associated | Insulated-gate field-effect transistors and their manufacture |
| EP0171003A2 (en) * | 1984-07-27 | 1986-02-12 | Hitachi, Ltd. | Field effect transistor with composite drain region |
| EP0197501A2 (en) * | 1985-04-12 | 1986-10-15 | General Electric Company | Extended drain concept for reduced hot electron effect |
| EP0198336A2 (en) * | 1985-04-12 | 1986-10-22 | General Electric Company | Hybrid extended drain concept for reduced hot electron effect |
| EP0198335A2 (en) * | 1985-04-12 | 1986-10-22 | General Electric Company | Graded extended drain concept for reduced hot electron effect |
| US4819043A (en) * | 1985-11-29 | 1989-04-04 | Hitachi, Ltd. | MOSFET with reduced short channel effect |
| EP0588320A2 (en) * | 1992-09-17 | 1994-03-23 | Hitachi, Ltd. | Semiconductor device having planar junction |
| GB2282262A (en) * | 1993-01-29 | 1995-03-29 | Mitsubishi Electric Corp | Field effect transistor |
| EP0670604A2 (en) * | 1994-03-03 | 1995-09-06 | Xerox Corporation | MOS thin-film transistors with a drain offset region |
| US5471073A (en) * | 1993-01-29 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor and method for producing the field effect transistor |
| US5850093A (en) * | 1989-11-20 | 1998-12-15 | Tarng; Huang Chang | Uni-directional flash device |
| CN110226218A (en) * | 2017-02-03 | 2019-09-10 | 索尼半导体解决方案公司 | Transistor and manufacturing method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636585B2 (en) * | 1973-07-02 | 1981-08-25 | ||
| FR2284983A1 (en) * | 1974-09-13 | 1976-04-09 | Commissariat Energie Atomique | MOS transistor - with smoothly changing impurities concn from drain to substrate by electric field strength manipulation |
| JPS52156576A (en) * | 1976-06-23 | 1977-12-27 | Hitachi Ltd | Production of mis semiconductor device |
| JPS5368581A (en) * | 1976-12-01 | 1978-06-19 | Hitachi Ltd | Semiconductor device |
-
1978
- 1978-08-08 DE DE19782834724 patent/DE2834724A1/en not_active Withdrawn
-
1979
- 1979-08-07 GB GB7927555A patent/GB2027992B/en not_active Expired
- 1979-08-07 FR FR7920191A patent/FR2433240A1/en not_active Withdrawn
- 1979-08-08 JP JP10116579A patent/JPS5524497A/en active Pending
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2150348A (en) * | 1983-11-29 | 1985-06-26 | Philips Electronic Associated | Insulated-gate field-effect transistors and their manufacture |
| EP0171003A2 (en) * | 1984-07-27 | 1986-02-12 | Hitachi, Ltd. | Field effect transistor with composite drain region |
| EP0171003A3 (en) * | 1984-07-27 | 1987-04-22 | Hitachi, Ltd. | Field effect transistor with composite drain region |
| EP0197501A2 (en) * | 1985-04-12 | 1986-10-15 | General Electric Company | Extended drain concept for reduced hot electron effect |
| EP0198336A2 (en) * | 1985-04-12 | 1986-10-22 | General Electric Company | Hybrid extended drain concept for reduced hot electron effect |
| EP0198335A2 (en) * | 1985-04-12 | 1986-10-22 | General Electric Company | Graded extended drain concept for reduced hot electron effect |
| EP0198335A3 (en) * | 1985-04-12 | 1986-12-10 | General Electric Company | Graded extended drain concept for reduced hot electron effect |
| EP0197501A3 (en) * | 1985-04-12 | 1986-12-17 | General Electric Company | Extended drain concept for reduced hot electron effect |
| EP0198336A3 (en) * | 1985-04-12 | 1986-12-17 | General Electric Company | Hybrid extended drain concept for reduced hot electron effect |
| US4680603A (en) * | 1985-04-12 | 1987-07-14 | General Electric Company | Graded extended drain concept for reduced hot electron effect |
| US4819043A (en) * | 1985-11-29 | 1989-04-04 | Hitachi, Ltd. | MOSFET with reduced short channel effect |
| US5850093A (en) * | 1989-11-20 | 1998-12-15 | Tarng; Huang Chang | Uni-directional flash device |
| EP0588320A2 (en) * | 1992-09-17 | 1994-03-23 | Hitachi, Ltd. | Semiconductor device having planar junction |
| EP0588320A3 (en) * | 1992-09-17 | 1994-09-21 | Hitachi Ltd | Semiconductor device having planar junction |
| US5804868A (en) * | 1992-09-17 | 1998-09-08 | Hitachi, Ltd. | Semiconductor device having planar junction |
| GB2282262A (en) * | 1993-01-29 | 1995-03-29 | Mitsubishi Electric Corp | Field effect transistor |
| US5471073A (en) * | 1993-01-29 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor and method for producing the field effect transistor |
| GB2274944B (en) * | 1993-01-29 | 1997-04-23 | Mitsubishi Electric Corp | Field effect transistor and method for producing the field effect transistor |
| GB2282262B (en) * | 1993-01-29 | 1997-04-23 | Mitsubishi Electric Corp | Field effect transistor and method for producing the field effect transistor |
| EP0670604A2 (en) * | 1994-03-03 | 1995-09-06 | Xerox Corporation | MOS thin-film transistors with a drain offset region |
| EP0670604A3 (en) * | 1994-03-03 | 1996-09-25 | Xerox Corp | Thin film MOS transistor with an offset drain zone. |
| CN110226218A (en) * | 2017-02-03 | 2019-09-10 | 索尼半导体解决方案公司 | Transistor and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2433240A1 (en) | 1980-03-07 |
| JPS5524497A (en) | 1980-02-21 |
| DE2834724A1 (en) | 1980-02-14 |
| GB2027992B (en) | 1982-10-06 |
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| PCNP | Patent ceased through non-payment of renewal fee |