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GB2008821A - Improvements relating to Digital Computers - Google Patents

Improvements relating to Digital Computers

Info

Publication number
GB2008821A
GB2008821A GB7842889A GB7842889A GB2008821A GB 2008821 A GB2008821 A GB 2008821A GB 7842889 A GB7842889 A GB 7842889A GB 7842889 A GB7842889 A GB 7842889A GB 2008821 A GB2008821 A GB 2008821A
Authority
GB
United Kingdom
Prior art keywords
address
descriptor table
entry
virtual address
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7842889A
Other versions
GB2008821B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of GB2008821A publication Critical patent/GB2008821A/en
Application granted granted Critical
Publication of GB2008821B publication Critical patent/GB2008821B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The invention provides apparatus in a digital computer for translating a virtual address to a real address. The computer memory is divided into segments which may be contiguous or may be further divided into noncontiguous subsegments. The virtual address consists of three portions. The first portion SEG addresses an entry in a segment descriptor table, the entry containing a digit indicating whether the segment referred to is contiguous or subdivided. Two modes of operation are possible in accordance with the value of this digit. In the first mode the segment descriptor table entry contains a base address to which the contents of the second portion SUB of the virtual address are added to obtain a real address. In the second mode the segment descriptor table entry contains the base address of a subsegment descriptor table, and the second portion of the virtual address contains the address of an entry within the subsegment descriptor table so specified, which entry contains a real address. In either case the third portion DISPL of the virtual address constitutes a displacement which is concatenated with the real address so obtained. The segment descriptor table entries may contain a presence bit and a length field, and the subsegment descriptor table entries may contain a presence bit, and means may be provided for checking the virtual address against these to generate an interrupt in response to an invalid address. <IMAGE>
GB7842889A 1977-11-04 1978-11-02 Digital computers Expired GB2008821B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84853577A 1977-11-04 1977-11-04

Publications (2)

Publication Number Publication Date
GB2008821A true GB2008821A (en) 1979-06-06
GB2008821B GB2008821B (en) 1982-01-13

Family

ID=25303555

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7842889A Expired GB2008821B (en) 1977-11-04 1978-11-02 Digital computers

Country Status (6)

Country Link
JP (1) JPS5474636A (en)
CA (1) CA1119313A (en)
DE (1) DE2847737C2 (en)
FR (1) FR2408176A1 (en)
GB (1) GB2008821B (en)
IT (1) IT1100062B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466056A (en) * 1980-08-07 1984-08-14 Tokyo Shibaura Denki Kabushiki Kaisha Address translation and generation system for an information processing system
GB2136171A (en) * 1983-01-07 1984-09-12 Tandy Corp Computer memory management system
DE3438869A1 (en) * 1983-10-31 1985-05-09 Sun Microsystems, Inc., Mountain View, Calif. COMPUTER SYSTEM WITH ADDRESS CONVERSION
GB2191317A (en) * 1986-05-24 1987-12-09 Hitachi Ltd Accessing memory

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6017130B2 (en) * 1980-06-06 1985-05-01 日本電気株式会社 address control device
US4532586A (en) * 1981-05-22 1985-07-30 Data General Corporation Digital data processing system with tripartite description-based addressing multi-level microcode control, and multi-level stacks
GB8405491D0 (en) * 1984-03-02 1984-04-04 Hemdal G Computers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756243A (en) * 1969-09-17 1971-03-01 Burroughs Corp METHOD AND APPARATUS FOR PERFORMING AND DEAFFECTING SMALL SPACES OF A MEMORY TO A CALCULATOR PROGRAM.
US3764996A (en) * 1971-12-23 1973-10-09 Ibm Storage control and address translation
FR122199A (en) * 1973-12-17
US3938100A (en) * 1974-06-07 1976-02-10 Control Data Corporation Virtual addressing apparatus for addressing the memory of a computer utilizing associative addressing techniques
FR2315744A1 (en) * 1975-06-27 1977-01-21 Telemecanique Electrique Search circuit for data processor memory - scans in accordance with virtual address associative memory storing addresses of memory pages

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466056A (en) * 1980-08-07 1984-08-14 Tokyo Shibaura Denki Kabushiki Kaisha Address translation and generation system for an information processing system
US4550368A (en) * 1982-07-02 1985-10-29 Sun Microsystems, Inc. High-speed memory and memory management system
GB2136171A (en) * 1983-01-07 1984-09-12 Tandy Corp Computer memory management system
DE3438869A1 (en) * 1983-10-31 1985-05-09 Sun Microsystems, Inc., Mountain View, Calif. COMPUTER SYSTEM WITH ADDRESS CONVERSION
GB2149158A (en) * 1983-10-31 1985-06-05 Sun Microsystems Inc Memory management system
GB2191317A (en) * 1986-05-24 1987-12-09 Hitachi Ltd Accessing memory
GB2191317B (en) * 1986-05-24 1990-05-16 Hitachi Ltd A register access mechanism for a data processing system

Also Published As

Publication number Publication date
IT1100062B (en) 1985-09-28
FR2408176A1 (en) 1979-06-01
JPS6136264B2 (en) 1986-08-18
IT7829424A0 (en) 1978-11-03
DE2847737C2 (en) 1982-08-05
CA1119313A (en) 1982-03-02
DE2847737A1 (en) 1979-05-17
GB2008821B (en) 1982-01-13
JPS5474636A (en) 1979-06-14
FR2408176B1 (en) 1982-06-25

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 19981101