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GB2006522A - Improvements in or relating to wafers having microelectric circuit chips thereon - Google Patents

Improvements in or relating to wafers having microelectric circuit chips thereon

Info

Publication number
GB2006522A
GB2006522A GB7838588A GB7838588A GB2006522A GB 2006522 A GB2006522 A GB 2006522A GB 7838588 A GB7838588 A GB 7838588A GB 7838588 A GB7838588 A GB 7838588A GB 2006522 A GB2006522 A GB 2006522A
Authority
GB
United Kingdom
Prior art keywords
chips
xiyj
conductors
outputs
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7838588A
Other versions
GB2006522B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Secretary of State for Industry
Original Assignee
UK Secretary of State for Industry
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UK Secretary of State for Industry filed Critical UK Secretary of State for Industry
Priority to GB7838588A priority Critical patent/GB2006522B/en
Publication of GB2006522A publication Critical patent/GB2006522A/en
Application granted granted Critical
Publication of GB2006522B publication Critical patent/GB2006522B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A semiconductor wafer 10 comprises a plurality of undiced chips X1Y1XnYm each including, in addition to conventional circuits, control circuits for transferring signals from an input to one of a plurality of outputs, which are connected to different adjacent chips XiYj so that the chips can be tested serially, "bad" chips being disregarded, and a continuous chain of sound chips being built up. In order to increase the chain length, the outputs of chips XiYm on one edge of the wafer 10 are connected by conductors 12 to the inputs of chips XiY1 on the opposite edge, so that the chips XiYj effectively lie on a cylindrical surface. Similarly, by different connections of the conductors 12, and using further conductors 14, the chips XiYj may be made to effectively lie on a toroid or an endless helix. <IMAGE>
GB7838588A 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon Expired GB2006522B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB7838588A GB2006522B (en) 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB4089677 1977-10-03
GB7838588A GB2006522B (en) 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon

Publications (2)

Publication Number Publication Date
GB2006522A true GB2006522A (en) 1979-05-02
GB2006522B GB2006522B (en) 1982-01-27

Family

ID=26264533

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7838588A Expired GB2006522B (en) 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon

Country Status (1)

Country Link
GB (1) GB2006522B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0028091A1 (en) * 1979-10-18 1981-05-06 Sperry Corporation Fault detection in integrated circuit chips and in circuit cards and systems including such chips
WO1983002163A1 (en) * 1981-12-18 1983-06-23 Burroughs Corp Branched labyrinth wafer scale integrated circuit
US4471483A (en) * 1980-08-21 1984-09-11 Burroughs Corporation Branched labyrinth wafer-scale integrated circuit
FR2548443A2 (en) * 1983-06-30 1985-01-04 Telemecanique Electrique Enhancement to electric switches using an insulating screen which shears the arc appearing between the contacts
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer
EP0436337A2 (en) * 1989-12-22 1991-07-10 Raytheon Company Technique for simplified testing of semiconductor circuits

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0028091A1 (en) * 1979-10-18 1981-05-06 Sperry Corporation Fault detection in integrated circuit chips and in circuit cards and systems including such chips
US4471483A (en) * 1980-08-21 1984-09-11 Burroughs Corporation Branched labyrinth wafer-scale integrated circuit
WO1983002163A1 (en) * 1981-12-18 1983-06-23 Burroughs Corp Branched labyrinth wafer scale integrated circuit
JPS58502123A (en) * 1981-12-18 1983-12-08 バロース　コーポレーション Branch maze wafer scale integrated circuit
FR2548443A2 (en) * 1983-06-30 1985-01-04 Telemecanique Electrique Enhancement to electric switches using an insulating screen which shears the arc appearing between the contacts
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer
EP0436337A2 (en) * 1989-12-22 1991-07-10 Raytheon Company Technique for simplified testing of semiconductor circuits
EP0436337A3 (en) * 1989-12-22 1992-02-26 Raytheon Company Technique for simplified testing of semiconductor circuits

Also Published As

Publication number Publication date
GB2006522B (en) 1982-01-27

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 19980927