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GB1597838A - Line driver circuits - Google Patents

Line driver circuits Download PDF

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Publication number
GB1597838A
GB1597838A GB43653/77A GB4365377A GB1597838A GB 1597838 A GB1597838 A GB 1597838A GB 43653/77 A GB43653/77 A GB 43653/77A GB 4365377 A GB4365377 A GB 4365377A GB 1597838 A GB1597838 A GB 1597838A
Authority
GB
United Kingdom
Prior art keywords
primary winding
line driver
resistor
driver circuit
damping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB43653/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB43653/77A priority Critical patent/GB1597838A/en
Priority to ZA00785040A priority patent/ZA785040B/en
Priority to PT68642A priority patent/PT68642A/en
Priority to NZ188639A priority patent/NZ188639A/en
Priority to BR7806858A priority patent/BR7806858A/en
Publication of GB1597838A publication Critical patent/GB1597838A/en
Priority to KE3272A priority patent/KE3272A/en
Priority to SG48983A priority patent/SG48983G/en
Priority to HK317/83A priority patent/HK31783A/en
Priority to MY345/84A priority patent/MY8400345A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20Repeater circuits; Relay circuits
    • H04L25/22Repeaters for converting two wires to four wires; Repeaters for converting single current to double current
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/66Switching arrangements for passing the current in either direction at will; Switching arrangements for reversing the current at will
    • H03K17/661Switching arrangements for passing the current in either direction at will; Switching arrangements for reversing the current at will connected to both load terminals

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Electronic Switches (AREA)
  • Dc Digital Transmission (AREA)

Description

(54) IMPROVEMENTS IN LINE DRIVER CIRCUITS (71) We, THE PLESSEY COMPANY LIMITED, a British Companv of Vicarage Lane, Ilford, Essex IGI 4AQ, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to improvements in line driver circuits for use in digital line transmission systems.
The invention finds application in transmission systems using High Density Bipolar Number 3/Alternate Mark Inversion HDB3/AMI type transmission.
Details of HDB3 type coding can be found in Communication Networks for Computers by D.W. Davies and D.L.A. Barber published by John Wiley & Sons, on pages 170 and 171.
Known line driver circuits consume in the order of 120mA and often incur 50% mismatch conditions because of incompatible transformer loadings under signal and no signal line states.
Accordingly an aim of the present invention is to provide an improved line driver circuit consuming less power than known circuits and which does not suffer from mismatch conditions.
According to the present invention there is provided a line driver circuit for use in digital line transmission systems, the circuit being transformer coupled to the line, the transformer having a centre-tapped primary winding and a secondary winding; the circuit comprising a first signal controlled switching device connected to one side of the primary winding, a second signal controlled switching device connected to the opposite side of the primary winding and a signal damping network connected across the primary winding and arranged to operate in such a manner than when the first and second switching devices are idle no signal appears in the secondary winding and damping network presents a load to the primary winding to balance the primary winding with the loading of the secondary winding, whereas when the first switching device is activated a first damping network isolation device is activated and a first output signal is produced in the secondary winding and when the second switching device is activated a second damping network isolation device is activated and a second output signal of opposite polarity is produced in the secondary winding.
An exemplary embodiment of the invention will be described with reference to the accompanying drawing in which Figure 1 shows a line drive circuit according to the invention and Figure 2 shows various waveforms which occur at different points in the circuit shown in Figure 1.
Referring to Figures 1 and 2 waveform WFA is presented to the base of transistor TRI by way of resistor R6 and waveform WFB is presented to the base of transistor TR2 by way of resistor R7. The digital line output signal shown as waveform DLO will be produced at the output oftransformerTl designated DLO in accordance with the following truth table: WFA WFB DLO H L + L H - L L 0 All other states are inhibited A logic '1' is transmitted down the line when DLO is + or - and a logic '0' is transmitted when DLO is 0.
When a logic '0' is to be transmitted to the line both transistor TRI and TR2 are switched off by their respective WFA and WFB waveform being in the Low (L) state.
Accordingly zero voltage appear across points X and Y, the centre-tapped primary winding of the transformer Tl. Equal current flows through resistor R3 and R4 diodes D3 and D4 and resistor R5 of the damping network, causing diodes D3 and D4 to conduct. Diodes D3 and D4 remain in conduction for small variations in the transformer windings allowing overshoot and line reflections to be absorbed reducing the amount of crosstalk experienced. The amount of current allowed to flow through resistors R3 and R4 is limited by resistor R5 and the value of this is optimised for lowest possible current, consistent with an adequate level of damping.When current flows through resistors R3 and R4 the resistors are effectively connected across the primary winding and their values are such that they present a load of4xR1 across the centre-tapped primary winding of transformer T1. The transformer windings are, therefore, correctly matched and mismatch conditions are prevented from occurring.
When a logic '1' is to be transmitted to the line either transistor TRI or TR2 is made to conduct by either waveform WFA or waveform WFB going to the high (H) state and accordingly either diode D3 or D4 is biased off. Resistors R3 and R4 are no longer in series across the centre-tapped primary winding of transformer Tl and therefore the damping circuit is not active.
An increased amount of current will pass through resistor R5 and the conducting resistor-diode combination, either resistor R3 and diode D3 or resistor R4 and diode D4 causing a slight loss of power.
Resistors RI and R2 are provided as line matching loads for transistors TRI and TR2 respectively and diodes Dl and D2 shunt the respective collectors of transistors TRI and TR2 respectively to earth for surge protection. Resistors R6 and R7 are in the order of 1 Kohms and allow the circuit to be driven from low power schottky transistortransistor logic.
The above description has been of one embodiment only and is not intended to limit the scope of the invention. Alternative arrangements will readily be seen by those skilled in the art, for example the value of resistor R5 can be varied to alter the damping threshold. The line driver circuit can be used in pulse code modulated systems.
WHAT WE CLAIM IS: 1. A line driver circuit for use in digital line transmission systems, the circuit being transformer coupled to the line, the transformer having a centre-tapped primary winding and a secondary winding; the circuit comprising a first signal controlled switching device connected to one side of the primary winding, a second signal controlled switching device connected to the opposite side of the primary winding and a signal damping network connected across the primary winding and arranged to operate in such a manner that when the first and second switching devices are idle no signal appears in the secondary winding and the damping network presents a load to the primary winding to balance the primary winding with the loading of the secondary winding, whereas when the first switching device is activated a first damping network isolation device is activated and a first output signal is produced in the secondary winding and when the second switching device is activated a second damping network isolation device is activated and a second output signal of opposite polarity is produced in the secondary winding.
2. A line driver circuit according to claim I in which the first and second signal controlled switching devices are transistors.
3. A line driver circuit according to claim I or 2 in which the first and second damping network isolation devices are diodes.
4. A line driver circuit according to claim 2 in which each transistor has an associated diode connected across their respective collector and base to provide surge protection for the transistors.
5. A line driver circuit as claimed in claim 3 in which the diodes have their positive end commoned and connected to earth by way of a resistor the resistance value of which determines the threshold of the damping network.
6. A line driver circuit substantially as described herein with reference to the accompanying drawing.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (6)

**WARNING** start of CLMS field may overlap end of DESC **. and the value of this is optimised for lowest possible current, consistent with an adequate level of damping. When current flows through resistors R3 and R4 the resistors are effectively connected across the primary winding and their values are such that they present a load of4xR1 across the centre-tapped primary winding of transformer T1. The transformer windings are, therefore, correctly matched and mismatch conditions are prevented from occurring. When a logic '1' is to be transmitted to the line either transistor TRI or TR2 is made to conduct by either waveform WFA or waveform WFB going to the high (H) state and accordingly either diode D3 or D4 is biased off. Resistors R3 and R4 are no longer in series across the centre-tapped primary winding of transformer Tl and therefore the damping circuit is not active. An increased amount of current will pass through resistor R5 and the conducting resistor-diode combination, either resistor R3 and diode D3 or resistor R4 and diode D4 causing a slight loss of power. Resistors RI and R2 are provided as line matching loads for transistors TRI and TR2 respectively and diodes Dl and D2 shunt the respective collectors of transistors TRI and TR2 respectively to earth for surge protection. Resistors R6 and R7 are in the order of 1 Kohms and allow the circuit to be driven from low power schottky transistortransistor logic. The above description has been of one embodiment only and is not intended to limit the scope of the invention. Alternative arrangements will readily be seen by those skilled in the art, for example the value of resistor R5 can be varied to alter the damping threshold. The line driver circuit can be used in pulse code modulated systems. WHAT WE CLAIM IS:
1. A line driver circuit for use in digital line transmission systems, the circuit being transformer coupled to the line, the transformer having a centre-tapped primary winding and a secondary winding; the circuit comprising a first signal controlled switching device connected to one side of the primary winding, a second signal controlled switching device connected to the opposite side of the primary winding and a signal damping network connected across the primary winding and arranged to operate in such a manner that when the first and second switching devices are idle no signal appears in the secondary winding and the damping network presents a load to the primary winding to balance the primary winding with the loading of the secondary winding, whereas when the first switching device is activated a first damping network isolation device is activated and a first output signal is produced in the secondary winding and when the second switching device is activated a second damping network isolation device is activated and a second output signal of opposite polarity is produced in the secondary winding.
2. A line driver circuit according to claim I in which the first and second signal controlled switching devices are transistors.
3. A line driver circuit according to claim I or 2 in which the first and second damping network isolation devices are diodes.
4. A line driver circuit according to claim 2 in which each transistor has an associated diode connected across their respective collector and base to provide surge protection for the transistors.
5. A line driver circuit as claimed in claim 3 in which the diodes have their positive end commoned and connected to earth by way of a resistor the resistance value of which determines the threshold of the damping network.
6. A line driver circuit substantially as described herein with reference to the accompanying drawing.
GB43653/77A 1977-10-20 1977-10-20 Line driver circuits Expired GB1597838A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
GB43653/77A GB1597838A (en) 1977-10-20 1977-10-20 Line driver circuits
ZA00785040A ZA785040B (en) 1977-10-20 1978-09-05 Improvements in line driver circuits
PT68642A PT68642A (en) 1977-10-20 1978-10-10 Improvements in line driver circuits
NZ188639A NZ188639A (en) 1977-10-20 1978-10-12 Line driver switching circuit
BR7806858A BR7806858A (en) 1977-10-20 1978-10-17 LINE DRIVER CIRCUIT
KE3272A KE3272A (en) 1977-10-20 1983-03-08 Improvements in line driver circuits
SG48983A SG48983G (en) 1977-10-20 1983-08-10 Improvements in line driver circuits
HK317/83A HK31783A (en) 1977-10-20 1983-08-25 Improvements in line driver circuits
MY345/84A MY8400345A (en) 1977-10-20 1984-12-30 Improvements in line driver circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB43653/77A GB1597838A (en) 1977-10-20 1977-10-20 Line driver circuits

Publications (1)

Publication Number Publication Date
GB1597838A true GB1597838A (en) 1981-09-09

Family

ID=10429722

Family Applications (1)

Application Number Title Priority Date Filing Date
GB43653/77A Expired GB1597838A (en) 1977-10-20 1977-10-20 Line driver circuits

Country Status (9)

Country Link
BR (1) BR7806858A (en)
GB (1) GB1597838A (en)
HK (1) HK31783A (en)
KE (1) KE3272A (en)
MY (1) MY8400345A (en)
NZ (1) NZ188639A (en)
PT (1) PT68642A (en)
SG (1) SG48983G (en)
ZA (1) ZA785040B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2567702A1 (en) * 1984-07-13 1986-01-17 France Etat Constant-current transmitter for transmitting data over a transmission line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2567702A1 (en) * 1984-07-13 1986-01-17 France Etat Constant-current transmitter for transmitting data over a transmission line

Also Published As

Publication number Publication date
PT68642A (en) 1978-11-01
NZ188639A (en) 1981-04-24
MY8400345A (en) 1984-12-31
ZA785040B (en) 1979-08-29
KE3272A (en) 1983-04-22
SG48983G (en) 1985-03-08
BR7806858A (en) 1979-07-17
HK31783A (en) 1983-09-02

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Legal Events

Date Code Title Description
PS Patent sealed
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee