GB1590031A - Means and method for recording seismic signals - Google Patents

Description

(54) MEANS AND METHOD FOR RECORDING SEISMIC SIGNALS (71) We, TEXACO DEVELOPMENT CORPORATION, a corporation organised and existing under the laws of the State of Delaware, United States of America, of 135 East 42nd Street, New York, New York 10017, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present system and method relates to amplifying systems and methods in general and, more particularly, to a floating point amplifier system and method.

The present invention provides a seismic system including an amplifying channel which receives a wide dynamic range input signal. The amplifying channel provides a plurality of amplified signals each having a different gain with respect to the input signal. Comparators compare each amplified signal, except for the least amplitude amplified signal, with reference signals corresponding to a predetermined range for an output signal. The comparators provide a plurality of outputs in accordance with the comparisons. A logic circuit processes the comparison signals to provide sampling pulses. Switches receiving the amplified signals from the amplifying channel are controlled by the sampling pulses to sample the amplified signals to provide the analog output in accordance with the comparison signals.An analog-to-digital converter network receives the gain signal and the analog output and provides digital signals, some of which correspond to the gain signal while the remaining digital signals correspond to the polarity and magnitude of the analog output.

The objects and advantages of the invention will appear more fully hereinafter, from a consideration of the detailed description which follows, taken together with the accompanying drawings, wherein several embodiments are illustrated by way of example.

Figure 1 is a simplified block diagram of a seismic recording system constructed in accordance with one embodiment of the present invention; Figure 2 is a simplified block diagram of a level comparator and a rate comparator which may be used with the system shown in Figure 1 to provide another embodiment of the present invention; Figure 3 is a simplified block diagram of a seismic recording system constructed in accordance with yet another embodiment of the present invention; Figure 4 is a detailed block diagram of the chopper stabilized floating point amplifier shown in Figure 3; and Figure 5 is a waveform diagram of control signals used in the amplifier of Figure 4.

In Figure 1 there is shown a seismic signal processing and recording system, including a plurality of geophones, gl, g2, gn indicating the presence of a plurality of such acoustic-toelectric transducer devices as determined by the particular practice in the art, for example, 12 or 24 or some other number thereof. Each of these geophones may in actuality comprise a group or cluster or a plurality of individual geophone instruments, with the respective outputs coupled together to provide a common geophone signal.

In Figure 1, the respective geophones gl, g2 and gn are shown coupled to the input portions of respective signal channels identified as channels 1, 2 and n respectively. Channels 1 through n are substantially identical, so that a description of channel 1 is also applicable to any other channel. Three channels are shown in the illustrated embodiment; it is to be understood that channel n is represented by one or more of such channels and that, in most cases, seismic signal process systems of the type described, comprise 12, 24 or larger number of channels.

Channel 1 comprises a plurality of amplifier stages, A and B1 through B4 directly coupled, e.g. DC coupled, to one another in cascade circuit relationship, with coupling networks C1 through C4. A feedback circuit, including the circuit elements within the dashed box identified as 0 is provided from the output of the last cascade stage B4 to the input of the first cascade stage Bl and the feedback circuit 0 includes an active filter N having a high frequency roll off characteristic and characteristic gain of at least unity. The N portion of the feedback circuit 0 is a network of resistors and capacitors, the values of which may be selected to provide the desired frequency characteristic of feedback circuit 0.An active stage comprising an operational amplifier M, provided for in the aforementioned feedback loop feedback circuit 0, should have a gain of at least unity and for the present embodiment has a positive gain of unity.

It is to be understood that a negative gain of at least minus one may be chosen, in which event it will be necessary to make an appropriate change in the manner of supplying feedback to the input of the cascade network in order to assure injection of the feedback in proper phase relationship with the input signal.

The details of amplifiers A, B1 through B4 and coupling networks C1 through C4 are shown in detail and described in U.S. Patent 3,562,744 which issued February 9, 1971. The output of each amplifier is applied to each buffer amplifier of amplifiers D1 through D5. Each buffer amplifier of amplifiers D1 through D5 functions as an isolation stage separating the respective outputs of amplifiers A through B4 from the signal input of a corresponding switching network schematically shown as blocks El through E5.

A multiplexer control unit 1 provides control signals V1, V2 and Vn in time relationship to each other. Control signal V1 is applied to switches El through E5 in channel 1 while control signal V2 is applied to switches El through E5 in channel 2 and control signal Vn is applied to switches El through E5 in channel n. Voltage V1 renders switches El through E5 in channel 1 conductive to pass the buffer amplifiers D1 through D5 to unity gain buffer amplifiers F1 through F5.Each buffer amplifier of buffer amplifiers F2 - F5 has its output connected to a corresponding level comparator LC1 through LC4, and each one of amplifiers F1 - F5 has its output connected to a corresponding switch G1 through G5. The outputs from level comparators LCl through LC4 are applied to inverters H1 through H4, respectively. The output from level comparator LC1 is also applied to a storage register 15 while the outputs from level comparators LC2 through LC4 are also applied to AND gates 7, 8 and 9, respectively.

The outputs from inverters Hlthrough H4 are applied to AND gates 7, 8 and 9 to storage register 15, respectively.

Comparators LC1 through LC4, AND gates 7, 8 and 9, and inverters H1 through H4 determine which of the outputs from amplifiers F1 through F5 is the greatest voltage which does not exceed the full scale level of an analog-todigital converter and digital control logic 10 hereinafter referred to as converter 10.

Flip-flop storage register 15 provides sampling pulses S1 through S5 to control switches G1 through G5 to pass a sample of the greatest value signal from amplifiers F1 through F5 which does not exceed full scale of converter 10. It should be noted that only one of these switches will be activated at any one time by storage register 15.

In a typical five gain range per channel embodiment, the system channel analog sample rate is at 1-millisecond intervals for a 32channel system or at 32-kilocycle sampling rate.

Assuming for example purposes only that the output from buffer amplifier F3 provides the maximum signal which does not exceed the full scale limits of converter 10, storage register 15 will provide a sampling pulse S3 rendering switch G3 conductive to pass the signal to amplifier 11 for the duration of sampling pulse S3 which in turn provides it to converter 10. Switches G1 through G5 are also connected to common output amplifier 11 and controlled in a similar manner.

At a. time slightly before converter 10 sampling time an enter pulse is provided by converter 10 to enter the outputs provided by level comparator LCl, inverter H4 and AND gates 7, 8 and 9 into storage register 15.

The control signals from storage register 15 also drive an encoder 16 which provides a three bit binary number to converter 10, corresponding to the gain level to be recorded, along with the value of analog signal provided by amplifier 11. Encoder 16 also receives signals from amplifiers A in each channel which indicate the gain which each of those amplifiers is set at. Encoder 16 provides the three bit binary numbers as the sum of the log of the gain of A and the log of the gain selected by storage register 15 for a particular channel.

Converter 10 converts the analog signal provided by amplifier 11 to a digital signal and provides the digital signal along with the three bit binary signal to digital tape recorder 20 where they are recorded on tape. Converter 10 also provides an advance pulse AP and a reset pulse to multiplexer control unit 1. The advance pulses AP cause multiplexer control unit 1 to provide signals V1 through Vn in seauence.

The signal from amplifier 11 may change at too fast a rate for converter 10 to accurately sample. This problem is solved by modification of the level comparators to make them responsive to the rate of the changing signal from amplifier 11 as well as to the absolute value of the signal from amplifier - such as amplifier F2, which is done with the type of level comparator shown in Figure 2.

The added portion, labelled rate comparator in Figure 2, comprises a slope detector 40 receiving the signal from amplifier F2, comparators 30A, 31 A and source 35A providing reference voltages V8, V9. Voltages V8, Vg define limits for the rate of change of the signal from amplifier F2. The outputs from comparators 30A, 31 A are applied to OR gate 36. Thus, with the arrangement shown in Figure 2, level comparator LC1 can provide a low level output from gate 36 when the rate of change of signal from amplifier F1 lies within the range defined by voltages V8 and Vg.

The level comparator LC1 shown in Figure 2 also includes reference comparators 30 and 31 receiving the signal from amplifier F2, and reference voltage source 35 providing reference voltages V6, V7. Voltages V6, V7 define a voltage range corresponding to the full scale range for converter 10.

When the signal from amplifier F2 is within the limits defined by voltages V6, V7, OR gate 36 can provide a low level output. Should the signal from amplifier F2 exceed one of the limits defined by voltages V6, V7, one of the comparators 30 or 31 provides a high level signal causing OR gate 36 to provide a high level output, whether or not the F2 signal rate of change is within the limits defined by voltages V8, Vg.

Thus, level comparator LCl provides a high level output when the amplitude of the signal from amplifier F1 is not within the range defined by voltages V6, V7 or the rate of change of the signal from amplifier F1 exceeds one of the limits defined by voltages V8, Vg.

Level comparators LC2, LC3 and LC4 would be of a similar type as level comparator LC1.

Referring now to Figure 3, there is again shown a plurality of channels 1 through n, with each channel including a high line balancing circuit 50 receiving an input signal from a corresponding geophone, an input transformer 51, preamplifier 53, a low pass filter 57, a high pass filter 59 and alais filter 62, a switch 65 are connected in series. Preamplifiers 53 through 53n also provide signals P1 through Pn related to their gain to broad band chopper stabilized floating point amplifier 70, hereinafter referred to as floating point amplifier 70. Floating point amplifier 70 which will be discussed in detail hereinafter also receives the signal passed by switches 65 through 65n, as the Q signal.The gain of preamplifier 53 is normally adjusted manually to give an overall predetermined gain to each channel shown in Figure 3 as determined by the operation of the system to be discussed in detail hereafter. However, in a preferred embodiment the gain of elements 50 through 62 should be BK, so that K could be added to (or subtracted from) the exponent determined by the following states of the channel. One embodiment of the system uses a value of K equal to unity (K=1.000 and B=8).

Switches 65 through 65n are controlled in multiplexing fashion by control signals U through Un provided by floating point amplifier 70. Floating point amplifier 70 provides gain coded digital signals corresponding to the exponent to converter 10 which also receives a signal W, corresponding to the amplified seismic signal, from amplifier 70. Converter 10 provides digital signals corresponding to the exponent and W signal to tape recorder 20 for recording.

Referring now to Figure 4, floating point amplifier 70 includes a single pole double throw electronic switch 80 having one input receiving the Q signal from switches 65 through 65n and another input connected to ground and cor trolled by a signal Z1 (shown in Figure 5) from chopper switch control logic 83 to alternately ground the Q signal and pass the Q signal to amplifier B1.Amplifiers B1 through B4, blocks C2 through C4, drivers D1 through D4, level comparators LC1 through LC4, switches G1 through G5, inverters H1 through H4, AND gates 7, 8 and 9, storage register 15, encoder 16 and amplifier 11 cooperate in the same manner as hereinbefore described (omitting switches El through E5 and amplifiers F1 through F5) to provide the signal W.

The output of amplifier B4 is also provided to a single pole single throw switch 88 which connects amplifier B4 to feedback network 0.

Switch 88 is controlled by a signal Z2 (shown in Figure 5) from chopper switch control logic 83. The sequence is such that the switch 80 passes the Q signal from swtiches 65 through 65n to series connected amplifiers B1 through B4 where it is amplified as hereinbefore described, while switch 88 blocks the output from amplifier B4 so as to not provide feedback to amplifier Bl. Switch 80 is then controlled by signal Z1 from the control logic 83 to effectively ground the output of amplifier B1 so that the output from amplifier B4 is substantially at zero level. Then later in time, switch 88 is controlled by signal Z2 from control logic 83 to pass the output of amplifier B4 to element 0, which provides a feedback signal to amplifier B1, for a predetermined time period.After the predetermined time period has ended, signal Z1 controls switch 80 to pass the Q signal to amplifier B1. In summary with each multiplexing cycle, the Q signal from a switch of switches 65 through 65n is applied to amplifier B1 for approximately half of the cycle. During the half cycle, the Q signal is not applied to amplifier B1, an error feedback voltage is applied to the 0 network by amplifier B4.

The system and method of the present invention as hereinbefore described provides a seismic recording system in which the amplified signals corresponding to an analog input signal are simultaneously compared with reference signals to provide a rapid selection and sampling of an amplified signal to provide an analog output, and converting means for converting the analog output to digital signals corresponding to a gain relationship between the analog output and the analog input signal. The system and method of the present invention also provides for multiplexing of several channels. The system further includes a network for providing rate of signal change comparison as well as amplitude comparison.

WHAT WE CLAIM IS: 1. An amplification system comprising amplifying channel means for amplifying a received analog input signal to provide amplified signals of different amplitudes, level comparing means for comparing each amplified signal,

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (12)

**WARNING** start of CLMS field may overlap end of DESC **. by voltages V8 and Vg. The level comparator LC1 shown in Figure 2 also includes reference comparators 30 and 31 receiving the signal from amplifier F2, and reference voltage source 35 providing reference voltages V6, V7. Voltages V6, V7 define a voltage range corresponding to the full scale range for converter 10. When the signal from amplifier F2 is within the limits defined by voltages V6, V7, OR gate 36 can provide a low level output. Should the signal from amplifier F2 exceed one of the limits defined by voltages V6, V7, one of the comparators 30 or 31 provides a high level signal causing OR gate 36 to provide a high level output, whether or not the F2 signal rate of change is within the limits defined by voltages V8, Vg. Thus, level comparator LCl provides a high level output when the amplitude of the signal from amplifier F1 is not within the range defined by voltages V6, V7 or the rate of change of the signal from amplifier F1 exceeds one of the limits defined by voltages V8, Vg. Level comparators LC2, LC3 and LC4 would be of a similar type as level comparator LC1. Referring now to Figure 3, there is again shown a plurality of channels 1 through n, with each channel including a high line balancing circuit 50 receiving an input signal from a corresponding geophone, an input transformer 51, preamplifier 53, a low pass filter 57, a high pass filter 59 and alais filter 62, a switch 65 are connected in series. Preamplifiers 53 through 53n also provide signals P1 through Pn related to their gain to broad band chopper stabilized floating point amplifier 70, hereinafter referred to as floating point amplifier 70. Floating point amplifier 70 which will be discussed in detail hereinafter also receives the signal passed by switches 65 through 65n, as the Q signal.The gain of preamplifier 53 is normally adjusted manually to give an overall predetermined gain to each channel shown in Figure 3 as determined by the operation of the system to be discussed in detail hereafter. However, in a preferred embodiment the gain of elements 50 through 62 should be BK, so that K could be added to (or subtracted from) the exponent determined by the following states of the channel. One embodiment of the system uses a value of K equal to unity (K=1.000 and B=8). Switches 65 through 65n are controlled in multiplexing fashion by control signals U through Un provided by floating point amplifier 70. Floating point amplifier 70 provides gain coded digital signals corresponding to the exponent to converter 10 which also receives a signal W, corresponding to the amplified seismic signal, from amplifier 70. Converter 10 provides digital signals corresponding to the exponent and W signal to tape recorder 20 for recording. Referring now to Figure 4, floating point amplifier 70 includes a single pole double throw electronic switch 80 having one input receiving the Q signal from switches 65 through 65n and another input connected to ground and cor trolled by a signal Z1 (shown in Figure 5) from chopper switch control logic 83 to alternately ground the Q signal and pass the Q signal to amplifier B1.Amplifiers B1 through B4, blocks C2 through C4, drivers D1 through D4, level comparators LC1 through LC4, switches G1 through G5, inverters H1 through H4, AND gates 7, 8 and 9, storage register 15, encoder 16 and amplifier 11 cooperate in the same manner as hereinbefore described (omitting switches El through E5 and amplifiers F1 through F5) to provide the signal W. The output of amplifier B4 is also provided to a single pole single throw switch 88 which connects amplifier B4 to feedback network 0. Switch 88 is controlled by a signal Z2 (shown in Figure 5) from chopper switch control logic 83. The sequence is such that the switch 80 passes the Q signal from swtiches 65 through 65n to series connected amplifiers B1 through B4 where it is amplified as hereinbefore described, while switch 88 blocks the output from amplifier B4 so as to not provide feedback to amplifier Bl. Switch 80 is then controlled by signal Z1 from the control logic 83 to effectively ground the output of amplifier B1 so that the output from amplifier B4 is substantially at zero level. Then later in time, switch 88 is controlled by signal Z2 from control logic 83 to pass the output of amplifier B4 to element 0, which provides a feedback signal to amplifier B1, for a predetermined time period.After the predetermined time period has ended, signal Z1 controls switch 80 to pass the Q signal to amplifier B1. In summary with each multiplexing cycle, the Q signal from a switch of switches 65 through 65n is applied to amplifier B1 for approximately half of the cycle. During the half cycle, the Q signal is not applied to amplifier B1, an error feedback voltage is applied to the 0 network by amplifier B4. The system and method of the present invention as hereinbefore described provides a seismic recording system in which the amplified signals corresponding to an analog input signal are simultaneously compared with reference signals to provide a rapid selection and sampling of an amplified signal to provide an analog output, and converting means for converting the analog output to digital signals corresponding to a gain relationship between the analog output and the analog input signal. The system and method of the present invention also provides for multiplexing of several channels. The system further includes a network for providing rate of signal change comparison as well as amplitude comparison. WHAT WE CLAIM IS:

1. An amplification system comprising amplifying channel means for amplifying a received analog input signal to provide amplified signals of different amplitudes, level comparing means for comparing each amplified signal,

except for the least amplitude amplified signal, with reference signals corresponding to a predetermined amplitude range for an analog output and providing a respective plurality of outputs, each output representative of a comparison of a different amplified signal with the reference signals, a plurality of switches, each switch receiving a different amplified signal and responsive to a different sampling pulse to pass the amplified signal as said analog output when the sampling pulse is present and to block the amplified signal during the absence of a sampling pulse; control means to provide at a predetermined rate sampling pulses in accordance with the outputs from the comparing means to the corresponding switches to cause the switches to pass successive samples of the appropriate amplified signal as the analog outputs; and converter means for providing digital signals corresponding to the gain relationship between the analog input signal and the actual analog output and to the polarity and magnitude of the actual analog output.

2. A system as claimed in Claim 1 wherein said level comparing means includes a plurality of level comparing networks, each said network receiving a different said amplified signal and includes first and second comparators to compare the pertinent amplified signal respectively with first and second range defining reference signals to provide said output representative of the comparison.

3. A system as claimed in Claim 2 including rate comparing means for comparing the rate of change of each amplified signal, except for the least amplitude amplified signal, with reference signals corresponding to a predetermined range of rate of change of amplitude and providing a respective plurality of outputs representative of the comparisons.

4. A system as claimed in Claim 3 wherein said rate comparing means includes a plurality of rate comparing networks, each said network receiving a different said amplified signal and comprising a rate detector for providing a rate signal corresponding to the rate of change with respect to time of the pertinent amplified signal, and third and fourth comparators for comparing the rate signal with the rate reference signals to provide said outputs representative of the comparison, and wherein said first, second, third and fourth comparators are connected to signal means to provide the output comparison signal in accordance with the outputs from those comparators.

5. A system as claimed in any one of Claims 1 to 4 wherein each amplifying channel means includes a series of cascade connected amplifier stages, the first amplifier stage in the cascade provides a signal representative of its gain, and feedback means connected to the output of the last amplifier stage for feeding back the signal to the input of the second amplifier stage.

6. A system as claimed in any one of Claims 1 to 5 including a plurality of said amplifying channel means for amplifying different received analog input signals each to provide a said set of amplified signals of different amplitudes; a plurality of switching means associated with each said channel means for receiving a multiplexing signal so as to pass the pertinent set of amplified signals to the pertinent plurality of switches and level comparing means when the multiplexing signal is of one amplitude and to block the set of amplified signals when the multiplexing signal is of another amplitude; and multiplexing means for providing the multiplexing signals to the switching means of one channel means at a time.

7. A system as claimed in any one of Claims 1 to 5 including a plurality of amplifier stages for amplifying different received analog input signals to provide respective amplified signals and gain signals, switching means connected respectively to the amplifier stages and receiving multiplexing signals for passing one said amplified signal at time in a sequential manner, and means connected to the switching means for providing the multiplexing signals, said sequentially passed amplified signals being passed to said amplifying channel means.

8. A system as claimed in Claim 7 wherein each amplifier stage includes a balancing circuit, a transformer connected to the balancing circuit, an amplifier for amplifying the output from the transformer and for providing a signal corresponding to the gain of the amplifier, a low pass filter, a high pass filter connected to the low pass filter, and an alais filter connected to the high pass filter for providing a filtered amplified signal to the switching means.

9. A system as claimed in Claim 8 including second switching means receiving the passed amplified signal from the first switching means and a switching signal for passing the passed amplified signal to either an input of the amplifying channel means or to ground in accordance with the switching signal, said second switching means also providing the passed amplified signal from the first switching means as the least amplitude amplified signal, third switching means connected to an output of the amplifying channel means and receiving a second switching signal for passing the amplified output signal when the second switching signal is of one amplitude, feedback means connecting the third switching means to another input of the amplifying channel means for feeding back the signal passed by the third switching means to the other said input, and means connected to the second and third switching means for providing the switching signals in a manner so as to alternately pass the passed amplified signal from the first switching means to the amplifying channel means and to ground and for feeding back the amplified signal to said other input of the amplifying channel means while the one input of the amplifying channel means is grounded.

10. A system as claimed in any one of Claims 1 to 5 including a group of geophones providing said analog signal to the amplifying channel means.

11. A system as claimed in any one of Claims 6 to 9 including a plurality of groups of geophones providing said different received analog signals for amplification.

12. An amplification system substantially as described herein with reference to Figures 1 and 2, or Figures 3 to 5, of the accompanying drawings.