GB1577713A - Printed circuit boards - Google Patents
Printed circuit boards Download PDFInfo
- Publication number
- GB1577713A GB1577713A GB14471/78A GB1447178A GB1577713A GB 1577713 A GB1577713 A GB 1577713A GB 14471/78 A GB14471/78 A GB 14471/78A GB 1447178 A GB1447178 A GB 1447178A GB 1577713 A GB1577713 A GB 1577713A
- Authority
- GB
- United Kingdom
- Prior art keywords
- wiring layer
- circuit board
- layer
- transverse
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims abstract description 128
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000012790 adhesive layer Substances 0.000 claims abstract description 35
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 238000000576 coating method Methods 0.000 claims abstract description 15
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 48
- 239000011888 foil Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000011889 copper foil Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- 238000003475 lamination Methods 0.000 claims description 9
- 238000004080 punching Methods 0.000 claims description 9
- 238000005476 soldering Methods 0.000 claims description 9
- 238000007650 screen-printing Methods 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 4
- 239000012777 electrically insulating material Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 150000001768 cations Chemical class 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000002035 prolonged effect Effects 0.000 claims description 2
- 238000003860 storage Methods 0.000 claims description 2
- 239000012876 carrier material Substances 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 239000013067 intermediate product Substances 0.000 description 5
- 238000004070 electrodeposition Methods 0.000 description 4
- 239000005011 phenolic resin Substances 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000000123 paper Substances 0.000 description 3
- 239000007858 starting material Substances 0.000 description 3
- 230000004308 accommodation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011087 paperboard Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0358—Resin coated copper [RCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/091—Locally and permanently deformed areas including dielectric material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/033—Punching metal foil, e.g. solder foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
This circuit board is intended to allow the electrically conductive transverse connection between the two wiring layers to be produced more simply and cheaply. To this end, the first wiring layer (3), an insulating adhesive layer (5) and the second wiring layer (9) are arranged successively on an insulating carrier material (1). A hole which passes through the second wiring layer (9) and the adhesive layer (5) is provided at the point of a transverse connection. The edge region of this hole is connected by means of a metal coating (12) to the region of the first wiring layer (3) which is exposed within the hole opening. The metal coating is formed by a solder or by an electroplated end surface. (11) designates a connecting pin. <IMAGE>
Description
(54) IMPROVEMENTS IN OR RELATING TO PRINTED
CIRCUIT BOARDS
(71) We, SIEMENS AKTIENGESELL
SCHAFT, a German Company of Berlin and
Munich, German Federal Republic, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to printed circuit boards having at least two wiring layers and at least one electrically conductive transverse connection between the two wiring layers, and to processes for the production of such printed circuit boards.
Printed circuit boards having two wiring layers and electrically conductive transverse connections between the two wiring layers are normally produced as a double-sided printed circuit with through-contacting holes passing through the circuit board. The procedure in this case is first to bore the holes in an electrically insulating carrier board covered with copper on both faces and then to electrolessly metallise the entire board, including the inner walls of the holes. After electrolytic reinforcement of the thin electroless metal deposit, photo-printing or silk-screen printing is used to provide an electrolytic-resistant covering of those parts of the metal layers on the board surfaces, which are later to be etched away. The conductor path patterns of the two sides of the board and the holes remain uncovered, and are provided with an etchresistant and simultaneously solderable and corrosion-resistant final metal surface by electrodeposition. Finally, after removal of the printing ink, the board is completed by etching away the exposed parts of the copper covering. This known process includes some steps which are very expensive to carry out. Thus, apart from the use of a high-grade carrier material, it is necessary to bore all the holes at the same time, in order to ensure that the walls of the holes have the quality required for through-contacting.
Moreover, the through-contacting is itself relatively expensive, since it necessitates the use of both electroless and electrolytic metallisation baths.
It is an object of the present invention to provide a printed circuit board having at least two wiring layers, wherein electrically conductive transverse connections between the two wiring lawers can be produced more cheaply and simply than in known arrangements.
According to the invention, there is provided a printed circuit board having at least two wiring layers on one face thereof and at least one transverse electrical connection between the wiring layers, and comprising an electrically insulating substrate board on one face of which there are successively arranged a first wiring layer, an electrically insulating adhesive layer, and a second wiring layer, a connection hole extending through said second wiring layer and said adhesive layer at the location of the or each transverse connection so as to expose a part of the surface of said first wiring layer therein, and a metal coating covering the inner wall of, but not filling, said connection hole and connecting at least the edge region of said second wiring layer surrounding said hole to the part of the surface of said first wiring layer exposed therein.
Thus, in the circuit board in accordance with the invention, at least two wiring layers are arranged closely adjacent to one another on one side only of the insulating carrier board. In this way, it is possible to dispense with the through-contacting holes passing through the board which were previously required. The or each electrically conductive transverse connection is established directly by means of a metal coating, so that the electroless metallisation step previously required can be dispensed with. A further advantage is provided by the close vicinity of the two wiring layers in the event of thermal loads, since in this case, the danger of breakage of the through-contacts which exists with conventional circuit boards owing to considerable expansion of the board under these circumstances in the direction at right-angles to the plane of the board, is avoided.
Advantageously, between the insulating carrier board and the insulating adhesive layer, those regions not occupied by the first wiring layer are filled up with an insulating material. This filling produces a board surface which is basically flat, so that in addition to an improved appearance, the printing processes required for the production of the second wiring layer are simplified.
In a prefererred form of circuit board in accordance with the invention, at the position of the or each transverse connection, there is arranged a further hole which passes through the first wiring layer and the insulating carrier board, the cross-sectional area of the further hole being smaller than that of the connecting hole passing through the second wiring layer and the adhesive layer, of which it forms a continuation. At the positions of the transverse connections, the combined holes provide openings which pass through the entire circuit board and which are suitable for the accommodation of terminal pins of components mounted on the board. The differing values of the crosssectional areas of the two holes provide an annular zone, the presence of which facilitates the transverse connection between the metal coatings of both the first and second wiring layers.
It is particularly advantageous if, in the connecting hole, the edge of the second wiring layer is turned over the edge of the adhesive layer, so that the two wiring layers are consequently brought more closely together at the location of the transverse connection, which further increases the reliability of the transverse connection established by the metal coating connecting thw two wiring layers in the connecting hole. The metal coating preferably consists of a solder. The electrically conductive transverse connection can then be established by a soldering process which is normally required anyhow. Since only the solder side of the circuit board is exposed and since this can be fully tinned during this soldering process, protection by means of an electrolytically deposited final surface layer can be dispensed with.
For the production of the circuit board of the present invention, two advantageous process variants can be used. In the first process, the first wiring layer is first produced on the insulating carrier board, a metal foil which is already provided with an insulating adhesive layer and is already perforated at the point or points where transverse connection is required, is then laminated onto the first wiring layer, the second wiring layer is then formed from the metal foil by a metalremoval technique, and finally the or each transverse connection is established by a soldering step. Thus, the production of the printed circuit board requires only low cost operating steps. In particular, all the transverse connections can be produced simultaneously in a single operation at the same time as the soldering-on of components.
In an alternative process, the first wiring layer is produced on the insulating carrier board, a metal foil which is already provided with an insulating adhesive layer and is perforated at the location of the or each transverse connection, is laminated onto the first wiring layer, the eletcrolytic metal deposition is then used to apply an etchresistant and solderable metal coating which produces the or each transverse connection and covers those areas of the metal foil which are required to form the second wiring layer, and the second wiring layer is then formed by etching from the metal foil by etching away the unprotected area. Thus, in this second process, a metal coating is applied electrolytically to form at the same time a final surface layer on the second wiring layer and functionally reliable, electrically conductive transverse connections. In the production of the second wiring layer by etching, this electrolytically deposited final surface layer can then be used as an etching reserve without the need for additional outlay. The transverse connections produced by the electrically deposited metal can also be considered as a preliminary transverse connection which is reinforced by the supply of solder during the subsequent soldering-on of components.
In both these processes, any known techinque, such as, for example, the additive technique, can be used to produce the first wiring layer. However, the first wiring layer is preferably formed by a subtractive technique (i.e. one involving the removal of metal) from a metal layer applied to the surface of the insulating carrier board.
The same subtractive technique can be used to form both the first and second wiring layers. Moreover, in this case, it is possible to use a cheap, commercially available carrier board covered with copper on one side, such as for example, a board made from phenol-resin impregnated paper.
Advantageously. before the application of the perforated metal foil by lamination, an eketrically insulating material is applied using silk-screen printing to those areas of the insulating carrier board surface which are not occupied by the first wiring layer.
This filling-in of the gaps employing silk screen printing requires only a low outlay and produces a flat board surface.
A further improvement in the functional reliability of the transverse connections can be achieved by perforating the metal foil, already provided with the adhesive layer, by punching it in such a way that in the hole the edge of the metal foil is turned outwardly over the edge of the adhesive layer.
If desired, in order to cause the two wiring layers to move even more closely together at the location of the transverse connections, the metal foil provided with the adhesive layer can be laminated onto the first wiring layer employing a pressure equalising foil.
Openings for the accommodation of the terminal pins of components mounted thereon, are preferably produced by a process in which, after the formation of the second wiring layer, at the location of the or each transverse connection, a further hole whose cross-sectional area is smaller than that of the connecting hole passing through the second wiring layer and the adhesive layer, is formed through the first wiring layer and the insulating carrier board.
The invention will now be further described with reference to the drawings, in which : - Figure 1 is a flow diagram of the process steps in a first process for the production of a printed circuit board in accordance with the invention;
Figures 2 and 3 are similar schematic side-sectional views of part of a printed circuit board to illustrate two successive steps in the process of Figure 1;
Figures 4 and 5 are similar schematic side-sectional views of part of a layer sequence for use in further successive steps in the process of Figure 1;
Figures 6 to 10 are similar views to those of Figures 1 and 2 to illustrate further successive steps in the process of Figure 1;
Figure 11 is a flow diagram of the process steps in a second process for the production of a printed circuit according to the invention;
Figures 12 and 13 are similar schematic side-sectional views of part of a printed circuit board to illustrate two successive steps in the process of Figure 11;
Figures 14 and 15 are similar schematic side-sectional views of part of a layer sequence for use in further successive steps of the process of Figure 11; and
Figures 16 to 20 are similar views to those of Figures 12 and 13 to illustrate further successive steps in the process of Figure 11.
Referring to the flow diaram of Figure 1 and the individual views of Figures 2 to 10, an electrically insulating carrier board 1 is provided on one side only with a copper covering 2, as shown in Figure 1. As the carrier board 1 does not have to meet stringent requirements, cheap materials, such as, for example, a board made from hardened phenol-resin impregnated paper, can be used. The thickness of such a phenol-resin impregnated paper board can, for example, be 1.6 mm, whilst a thickness of 35 ,am is suitable for the copper covering 2. Then, as shown in Figure 3, following a suitable mask, the desired conductor path pattern of the first wiring layer 3 is produced from the copper covering 2 by etching away the unrequired portions thereof.
As a second starting material, there is provided a copper foil 4 which is illustrated in Figure 4 and which may, for example, have a thickness of 35 pm and is covered on one side with a layer having a thickness of, for example, 50 /lem, of a heat-hardenable adhesive 5. A suitable material for use as the adhesive layer 5 is a phenol-butyral dry adhesive film such as that marketed by the Permacel Company of New Brunswick,
N.J. USA, under the Trade Name " Per macel Foil P18 ". Then, as shown in Figure 5, holes are punched into this adhesivecoated copper foil 4 at the positions where transverse connections are subsequently to be provided. In the punching of these holes 6, which may, for example, have a diameter of 1.4 mm, a punching needle is moved in the direction of the arrows 7 so that at the edges of the holes 6, the copper foil 4 is turned over towards the edges of the adhesive layer 5. This kind of flanging action is referred to as the " nozzle drawing effect" in punching technology.
The intermediate product illustrated in
Figure 5 is now laminated onto the intermediate product illustrated in Figure 3 by means of pressure and heat, care being taken to ensure a correct alignment of the two products, so that, as shown in Figure 6, the adhesive layer 5 is firmly connected to the first wiring layer 3 and to the exposed areas of the carrier material 1. When Permacel Foil P18 is used for the adhesive layer 5, the laminating process can be carried out, for example, at a pressure of 245 Nick2 and a temperature of 170"C. After 15 minutes, the laminate produced is cooled under pressure to about 50"C. Subsequently, a final hardening which lasts for about 15 minutes is carried out at a temperature of 1700C in a circulating air furnace. Expediently, during the lamination, between the two rams of the press used, an elastic pressure equalising foil 8, shown in dashdotted fashion in Figure 6, is placed on the copper foil 4, so that the edges of the holes 6 are pressed as closely as possible against the underlying, first wiring layer.
After the lamination step, as shown in
Figure 7, the desired conductor path pattern of the second wiring layer 9 is produced by etching away the unrequired portions of the copper layer 4, using a suitable mask.
As shown in Figure 8, holes 10 are then punched through the first wiring layer 3 and the carrier board 1 at the points provided for the transverse connections between the wiring layers. The holes 10 are arranged to be concentric with the holes 6 but to be of somewhat smaller diameter, so that an annular soldering lug formed in the first wiring layer 3 is left exposed. When the holes 6 have a diameter of 1.4 mm, the diameter of the holes 10 may, for example, be 1.0 mm.
After the punching in of the holes 10, the circuit board is equipped with the required components, the terminal pins 11 of the components being passed through the holes
10 and 6, as illustrated in Figure 9.
The transverse electrical connections are completed when the circuit board is finally soldered in a surge bath or dip bath, when, as is shown in Figure 10, the second wiring layer 9, the exposed solder lug rings of the first wiring layer 3, and the terminal pins 11 are wetted by a solder 12. The solder 12, which may, for example, be a tin-lead solder, thus establishes the functionally reliable, electrically transverse connections between the wiring layers 3 and 9, and simultaneously provides the second wiring layer 9 with a corrosion-resistant surface protection layer.
A second process for the production of a printed circuit board in accordance with the invention is shown as a flow sheet in Figure 11, the individual steps being illustrated in
Figures 12 to 20. A first intermediate product used as one starting material consists of a carrier board 21 which is illustrated in Figure 12 and which is provided on one face only with a copper covering 22. When the copper covering 22 has a thickness of 35 zm, a 1.6 mm thick phenol-resin impregnated hard paper is again suitable for the carrier board 21. Then, as shown in
Figure 13, using a suitable mask the desired conductor path pattern of the first wiring layer 23 is produced from the copper covering 22 by etching away the unrequired portions thereof. After the etching step, those areas of the covering 22 where the copper has been removed are filled up with an electrically insulating material 24, so as to form a flat surface. A suitable insulating material 24 is a silk-screen printable epoxy resin which is composed of two components and which is applied by silk-screen printing and, after a brief preliminary drying, is finally hardened at a temperature of about 1200C for a time of 20 to 30 minutes.
The second starting material consists of a copper foil 25 which is illustrated in Figure 14 and which may, for example, have a thickness of 35 lim and is covered on one face with a layer of a heat-hardenable adhesive 26, having a thickness of, for example, 50 jam. Then, as shown in Figure 15, holes 27 are punched into this adhesivecoated copper foil 25 at the positions required for the subsequent transverse connections. In the punching of these holes 27, which may, for example, have a diameter of 1.4 mm, a punching needle is moved in the direction of the arrows 28 so that as the edge of the holes 27, the copper foil 25 is turned over towards the edge of the adhesive layer 26.
The intermediate product illustrated in
Figure 15 is now laminated onto the intermediate product illustrated in Figure 13 using heat and pressure, care being taken to obtain accurate registration of the two products, so that the adhesive layer 26 is firmly joined to the first wiring layer 23 and to the insulating material 24. The conditions already described in respect of the first production process of Figure 1 can again be used for the lamination and the hardening of the adhesive layer 26.
After the lamination step, photo-printing or silk-screen printing is used to effect an electrodeposition-resistant covering of those parts of the copper foil 25 which are later to be etched away. An etch-resistant, solderable and corrosion-resistant outer surface 29 is then applied by electrodeposition to those areas of the copper foil 25 corresponding to the conductor path pattern of the second wiring layer, and to those regions of the first wiring layer 23 which are exposed within the holes 27. The second wiring layer 30 is then completed by removing the electrodeposition - resistant covering and etching away the exposed copper, as a result of which the arrangement shown in
Figure 17 is formed. The electrodeposited final surface 30, which may consist, for example, of a tin-lead solder, also establishes the electrically conductive transverse connections between the first wiring layer 23 and the second wiring layer 30 at the positions provided for this purpose. As can be seen from Figure 18, holes 31 are then punched through the first wiring layer 23 and the carrier board 21 at the positions of the transverse connections. The holes 31 are arranged so as to be concentric with the holes 27 but to be somewhat smaller in diameter, so that an annular soldering lug remains uncovered in the first wiring layer 23 around the hole and the through-contacts which have already been established are not broken. When the holes 27 have a diameter of 1.4 mm, the diameter of the holes 31 may, for example, be 1.0 mm.
After the punching of the holes 31, the circuit board is complete, and the good solderability is fully maintained even after prolonged storage. The circuit board is provided with components by, as shown in
Figure 19, passing the terminal pins 32 of the components through the holes 27 and 31. Finally, the soldering-in of the components is carrid out in a surge bath or dip bath, by means of which, as shown in Figure 20, the electrodeposited outer surface 29 and the terminal pins 32 are wetted by a solder 33. The solder 33, which may be, for example, a tin-lead solder, reinforces the transverse connections which have already bene produced by the electrodeposited outer surface layer 29.
The production of printed circuit boards having two wiring layers only has been described with reference to the drawings.
However, it is equally possible to produce circuit boards having three or more wiring layers in a corresponding manner. In order to form a third wiring layer, a further, adhesive-coated copper foil perforated at the required locations of the transverse connecillustrated in Figure 7. The holes which are introduced into this copper foil then only need to have a somewhat larger diameter than the holes 6 in the second wiring layer 9. After the lamination step, the third wiring layer can be produced from this further copper foil using a subtractive technique. The production of the electrically conductive transverse connections by means of a solder is then again carried out in the manner described, although, in this case, the solder connects three soldering lug rings in a stepped arrangement at the positions of the traneverse connections. In place of the solder, the electrically conductive transverse connections can alternatively be produced by an electrolytically deposited final surface layer applied to the third wiring layer.
WHAT WE CLAIM IS:- 1. A printed circuit board having at least two wiring layers on one face thereof and at least one transverse electrical connection between the wiring layers, and comprising an electrically insulating substrate board, on one face of which there are successively arranged a first wiring layer, an electrically insulating adhesive layer, and a second wiring layer, a connection hole extending through said second wiring layer and said adhesive layer at the location of the or each transverse connection so as to expose a part of the surface of said first wiring layer therein; and a metal coating covering the inner wall of, but not filling, said connection hole and connecting at least the edge region of said second wiring layer surrounding said hole to the part of the surface of said first wiring layer exposed therein.
2. A circuit board as claimed in Claim 1,
wherein between said insulating carrier
board and said adhesive layer those areas
of said first wiring layer not occupied by
the conductor path structure thereof are
filled with an electrically insulating material.
3. A circuit board as claimed in Claim
1 or Claim 2, wherein at the location of
the or each transverse connection, there is
arranged a further hole which passes
through said first wiring layer and said
carrier board and the cross-sectional area
of which is smaller than that of said con
necting hole.
4. A circuit board as claimed in any one
of the preceding Claims, wherein in the or
each said connecting hole, the edge of said
second wiring layer is turned over towards
the edge of said adhesive layer.
5. A circuit board as claimed in any one of the preceding Claims, wherein said metal
coating consists of a solder.
6. A printed circuit board as claimed in
Claim 1, substantially as hereinbefore de
scribed with reference to the drawings.
7. A process for the production of a
printed circuit board as claimed in Claim 1
comprising the steps of producing a first
wiring layer on one face of an electrically
insulating carrier board, laminating a metal
foil already provided with an electrically
insulating adhesive layer and perforated at
the location of the or each transverse con
nection to said first wiring layer, forming a
second wiring layer from said metal foil
employing a subtractive technique, and
thereafter establishing said transverse con
nection or connections by soldering.
8. A process for the production of a
printed circuit board as claimed in Claim 1,
comprising the steps of producing a first
wiring layer on one face of an electrically
insulating carrier board, laminating a metal
foil already provided with an electrically in- sulating adhesive layer and perforated at
the location of the or each transeverse con
nection to said first wiring layer, electro
depositing an etch-resistant and solderable
metal coating which produces said trans
verse connection or connections and covers
those areas of said metal foil corresponding
to the conductor path pattern of said second
wiring layer, and thereafter forming said
second wiring layer by etching said metal
foil.
9. A process as claimed in Claim 7 or
Claim 8, wherein said first wiring layer is
formed by means of a subtractive technique
from a metal covering applied to said face
of said carrier board.
10. A process as claimed in any one of
Claims 7 to 9, wherein prior to the appli
cation of said perforated metal foil to said
carrier board by lamination, an insulating
material is applied by silk-screen printing
to those regions of the carrier board which
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (15)
1. A printed circuit board having at least two wiring layers on one face thereof and at least one transverse electrical connection between the wiring layers, and comprising an electrically insulating substrate board, on one face of which there are successively arranged a first wiring layer, an electrically insulating adhesive layer, and a second wiring layer, a connection hole extending through said second wiring layer and said adhesive layer at the location of the or each transverse connection so as to expose a part of the surface of said first wiring layer therein; and a metal coating covering the inner wall of, but not filling, said connection hole and connecting at least the edge region of said second wiring layer surrounding said hole to the part of the surface of said first wiring layer exposed therein.
2. A circuit board as claimed in Claim 1,
wherein between said insulating carrier
board and said adhesive layer those areas
of said first wiring layer not occupied by
the conductor path structure thereof are
filled with an electrically insulating material.
3. A circuit board as claimed in Claim
1 or Claim 2, wherein at the location of
the or each transverse connection, there is
arranged a further hole which passes
through said first wiring layer and said
carrier board and the cross-sectional area
of which is smaller than that of said con
necting hole.
4. A circuit board as claimed in any one
of the preceding Claims, wherein in the or
each said connecting hole, the edge of said
second wiring layer is turned over towards
the edge of said adhesive layer.
5. A circuit board as claimed in any one of the preceding Claims, wherein said metal
coating consists of a solder.
6. A printed circuit board as claimed in
Claim 1, substantially as hereinbefore de
scribed with reference to the drawings.
7. A process for the production of a
printed circuit board as claimed in Claim 1
comprising the steps of producing a first
wiring layer on one face of an electrically
insulating carrier board, laminating a metal
foil already provided with an electrically
insulating adhesive layer and perforated at
the location of the or each transverse con
nection to said first wiring layer, forming a
second wiring layer from said metal foil
employing a subtractive technique, and
thereafter establishing said transverse con
nection or connections by soldering.
8. A process for the production of a
printed circuit board as claimed in Claim 1,
comprising the steps of producing a first
wiring layer on one face of an electrically
insulating carrier board, laminating a metal
foil already provided with an electrically in- sulating adhesive layer and perforated at
the location of the or each transeverse con
nection to said first wiring layer, electro
depositing an etch-resistant and solderable
metal coating which produces said trans
verse connection or connections and covers
those areas of said metal foil corresponding
to the conductor path pattern of said second
wiring layer, and thereafter forming said
second wiring layer by etching said metal
foil.
9. A process as claimed in Claim 7 or
Claim 8, wherein said first wiring layer is
formed by means of a subtractive technique
from a metal covering applied to said face
of said carrier board.
10. A process as claimed in any one of
Claims 7 to 9, wherein prior to the appli
cation of said perforated metal foil to said
carrier board by lamination, an insulating
material is applied by silk-screen printing
to those regions of the carrier board which
are not occupied by the conductor path pattern of said first wiring layer.
11. A process as claimed in any one of
Claims 7 to 10, wherein said metal foil provided with the adhesive layer is perforated by punching in such manner that the edge of the hole in said metal foil is turned over towards the edge of the hole in said adhesive layer.
12. A process as claimed in Claim 11, wherein said metal foil provided with said adhesive layer is laminated to said first wiring layer using a pressure equalising foil.
13. A process as claimed in any one of Claims 7 to 12, wherein after the formation of said second wiring layer, at the location of the or each transverse conneclion, a further hole having a cross-sectional area which is smaller than that of said connecting hole, is formed coaxially of said connecting hole so as to pass through said first wiring layer and said carried board.
14. A process for the production of a printed circuit board as claimed in Claim 1 substantially as hereinbefore described with reference to Figures 1 to 10, or Figures 11 to 20 of the drawings.
15. A printed circuit board produced by a process as claimed in any one of Claims 7 to 14.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19772716545 DE2716545A1 (en) | 1977-04-14 | 1977-04-14 | PRINTED CIRCUIT BOARD WITH AT LEAST TWO LAYERS OF WIRING |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1577713A true GB1577713A (en) | 1980-10-29 |
Family
ID=6006294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB14471/78A Expired GB1577713A (en) | 1977-04-14 | 1978-04-13 | Printed circuit boards |
Country Status (9)
Country | Link |
---|---|
JP (1) | JPS53128765A (en) |
BE (1) | BE866001A (en) |
CH (1) | CH628195A5 (en) |
DE (1) | DE2716545A1 (en) |
FR (1) | FR2387568A1 (en) |
GB (1) | GB1577713A (en) |
IT (1) | IT1096057B (en) |
NL (1) | NL7803993A (en) |
SE (1) | SE7804192L (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0062084A1 (en) * | 1981-04-06 | 1982-10-13 | Herbert Irwin Schachter | Multi-level circuit and method of making same |
US4915983A (en) * | 1985-06-10 | 1990-04-10 | The Foxboro Company | Multilayer circuit board fabrication process |
AU622100B2 (en) * | 1986-12-17 | 1992-04-02 | Foxboro Company, The | Multilayer circuit board fabrication process |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5797970U (en) * | 1980-12-08 | 1982-06-16 | ||
JPS60137092A (en) * | 1983-12-19 | 1985-07-20 | 株式会社東芝 | Circuit board |
JPS60140897A (en) * | 1983-12-28 | 1985-07-25 | 日本電気株式会社 | Resin insulated multilayer board |
DE4135839A1 (en) * | 1991-10-31 | 1993-05-06 | Huels Troisdorf Ag, 5210 Troisdorf, De | METHOD FOR PRODUCING A MULTILAYER PRINTED CIRCUIT AND MULTI-LAYER PRINTED CIRCUIT |
AT398877B (en) * | 1991-10-31 | 1995-02-27 | Philips Nv | TWO OR MULTILAYERED CIRCUIT BOARD, METHOD FOR PRODUCING SUCH A CIRCUIT BOARD AND LAMINATE FOR PRODUCING SUCH A CIRCUIT BOARD BY SUCH A PROCESS |
AT398876B (en) * | 1991-10-31 | 1995-02-27 | Philips Nv | TWO OR MULTILAYER PCB |
EP0744884A3 (en) * | 1995-05-23 | 1997-09-24 | Hitachi Chemical Co Ltd | Process for producing multilayer printed circuit board |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3528173A (en) * | 1966-08-15 | 1970-09-15 | Andrew S Gall | Making circuit boards |
-
1977
- 1977-04-14 DE DE19772716545 patent/DE2716545A1/en not_active Ceased
-
1978
- 1978-02-28 CH CH213678A patent/CH628195A5/en not_active IP Right Cessation
- 1978-04-04 FR FR7809924A patent/FR2387568A1/en active Granted
- 1978-04-10 IT IT22145/78A patent/IT1096057B/en active
- 1978-04-13 JP JP4375778A patent/JPS53128765A/en active Pending
- 1978-04-13 SE SE7804192A patent/SE7804192L/en unknown
- 1978-04-13 GB GB14471/78A patent/GB1577713A/en not_active Expired
- 1978-04-14 NL NL7803993A patent/NL7803993A/en not_active Application Discontinuation
- 1978-04-14 BE BE186806A patent/BE866001A/en unknown
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0062084A1 (en) * | 1981-04-06 | 1982-10-13 | Herbert Irwin Schachter | Multi-level circuit and method of making same |
US4915983A (en) * | 1985-06-10 | 1990-04-10 | The Foxboro Company | Multilayer circuit board fabrication process |
AU622100B2 (en) * | 1986-12-17 | 1992-04-02 | Foxboro Company, The | Multilayer circuit board fabrication process |
Also Published As
Publication number | Publication date |
---|---|
FR2387568B1 (en) | 1982-06-04 |
IT7822145A0 (en) | 1978-04-10 |
JPS53128765A (en) | 1978-11-10 |
DE2716545A1 (en) | 1978-10-19 |
IT1096057B (en) | 1985-08-17 |
SE7804192L (en) | 1978-10-15 |
CH628195A5 (en) | 1982-02-15 |
BE866001A (en) | 1978-07-31 |
NL7803993A (en) | 1978-10-17 |
FR2387568A1 (en) | 1978-11-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |