GB1570510A - Micro-programme controlled data processing systems - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO MICRO-PROGRAMME CONTROLLED DATA PROCESSING SYSTEMS (71) We, SIEMENS AKTIENGES ELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a micro-pro gramme controlled data processing system, and is particularly concerned with the processing therein of machine commands of different formats.

In small and medium-sized micro-programme controlled data processing systems purely sequential command processing is conventional in all standard central units, each machine command being firstly read out from the working store, then being interpreted so that all the requisite operands can be read out from registers or directly from working store zones, and then being executed in that the operands which have been made available are e.g. logic-linked and the result of the operation is re-written into a given point in the selected storage medium, i.e. register or working store zone.

The application of purely sequential command processing to larger data processing systems, however, results in undesirable out lay and complexity of the system. For example the data width of the interface between a processor and the working store can be increased in comparison to the format of the average machine command, so that it is possible to read out simultaneously a plurality of machine commands with one working store access, read-out machine commands or command components being intermediately stored before being made available for processing. In this manner it is possible to economise on store accesses for reading out machine commands approximately in a ratio corresponding to the breadth of the interface to the format of the average command. The organisation of the working store system, however, considerably limits the extent to which this measure can be exploited because it is not possible effectively and readily to increase the length of the working store words in arbitrary fashion. It is also known to classify each processor into a plurality of processing stations which may be arranged in several chains and may have special functions for the processing of machine commands. If the processing times in the individual processing stations of a chain are approximately equal, then the machine commands of a sequence of machine commands can pass consecutively through the individual processing stations. This measure, however, involves a high outlay and renders difficult the coordination of the working store accesses for the read-out of machine commands and for the read-out and write-in of specific store operands in the execution of the machine commands, for which coordination it is necessary to use an expensive instruction control unit.

It will be gathered from these known measures that it is basically possible to overlap the three phases of command read-out, command interpretation, and command execution. This invention seeks to provide an im- proved data processing system in which such overlapping occurs. In such a system the micro-programmes for the machine command which is to be executed and read-out accesses for following machine commands cannot be allowed to obstruct one another in the working store system. Furthermore these accesses should be coordinated in a simple fashion. The pre-loading of machine commands, i.e. a working store access for a following machine command, can not be allowed to lead to programme errors, which for example could be due to a machine command which has already been made available being modified in the working store system in the execution ef a preceding machine command. Such fault sources and other errors which occur during the readout access must be able to be recognised and corrected in a simple way.

According to this invention there is provided a data processing system comprising a processing unit arranged in operation to execute machine commands under microprogramme control, a store which serves to store the machine commands, a data register having a data width of one store word, an address register for addressing the store with a store address to write in thereto from and to read out therefrom to the data register in each case one store word, two command buffers each having the same data width as the data register and into which store words can be transferred from the data register, means arranged in operation to supply machine commands previously read out from the store selectively from the command buffers to the processing unit to be executed thereby, a first command counter which is arranged to contain an address indicative of the position in the store of the machine command which is about to be executed in the processing unit, a second command counter which is arranged to contain an address indicative of the position in the store of the latest machine command to be read out from the store, whereby a machine command is read out from the store and stored in the command buffers during the execution in the processing unit of a previous machine command, and comparator means arranged in operation during each write-in access to the store to compare the store address contained in the address register with the addresses contained in the command counters and to indicate whenever such a store access takes place in respect of store locations corresponding to commands already read-out but still awaiting execution.

Thus the provision of machine commands is effected directly in association with a micro-programme routine " provision of addresses and operands" which is executed in to; phase of the command interpretation, under tha control of a central micro-programme control unit Since the individual functions or elementary operations for a " read-out command" process must also be independently provided, this involves only a minimal additional outlay in the central micro-programme control unit, e.g. one bit position per microcommand. On the other hand, the aforementioned micro-programme component can be constructed in such a way that even in the event of different command formats and types, for the actual command interpretation in each case a series of elementary operations occur in which no working store access is necessary. In this way the access conflict can also be simply overcome. Additional advantages are provided in that little extra hardware is required in that it is readily possible to establish the validity of the contents of the command buffers.

The invention will be further understood from the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which: Fig. 1 shows in the form of a block circuit diagram of parts of a micro-programme con strolled data processing system for the read out, interpretation, and execution of commands; and Fig. 2 to 4 schematically illustrate the processing sequence of various types of command.

Referring to Fig. 1, 32 bit store words may be selected, one word at a time, from a working store ASP by means of a 24 bit address supplied by an address register MA which is connected to an address bus A-BUS.

In a read-out process the store word is entered into a 32 bit data register MD, and in a write-in process data is supplied via a data but D-BUS to this register MD from which it is entered into the store ASP.

The data register MD is connected to two command buffers (registers) PF1 and PF2 which likewise can each accommodate 32 bits, i.e. 4 bytes where 1 byte comprises 8 bits.

The command buffer PF1 receives 4 bytes in parallel from the data register MD and transfers 4 bytes in parallel to the second command buffer PF2 receives 4 bytes in parallel to a switch W1 or to a switch W2. The command buff PF2 receives 4 bytes in parallel from the command buffer PF1 and transfers 2 or 4 bytes in parallel to the switch W1, which also receives 4 bytes in parallel from the data register MD.

The command buffers PF1 and PF2 serve for intermediate storage of previously readout machine commands which, as will be explained in the following, can have a length of 2, 4, or 6 bytes in dependence upon their type. With this varying command format, a machine command stored in the working store ASP can be aligned to the word limit (4 bytes) or half-word limit (2 bytes).

The switches W1 and W2 serve to trans fer machine commands from the command buffers PF1 and PF2 to a processing unit EU. The switch W1 is a 4-byte switch which switches bytes through from the command buffers PF1 and PF2 to the processing unit EU, in dependence upon the alignment in the working store ASP of the previously read-out machine command to a word-limit or half word limit, as follows: If the machine con.- mand is aligned to a word limit, the 4 bytes contained in the command buffer PF2 are switched through via the switch W1 to the processing unit EU. Otherwise the switch W1 transfers to the processing unit EU the third and fourth bytes, contained in a second half PF2L, of the command buffer PF2, together with the first and second bytes, contained in a first half PF1H, of the command buffer PF1. The switch W2 is a 2-byte switch which, in the case of each machine command having a command format of 6 bytes, switches through 2 bytes from the command buffer PF1 to the processing unit EU. If in the working store ASP the command is aligned to a word limit, the first and second bytes, contained in the half PF1H, of the com mand buffer PF1 are transferred, otherwise the third and fourth bytes, contained in the second half PF1L of the command buffer PF1 are transferred. As noted above, the switch W1 is also capable of transferring data directly from the data register MD to the processing unit EU.

The processing unit EU is of conventional construction, as is the working store ASP and the central micro-programme control unit (not shown), and is not explained here in detail. Fig. 1 merely shows that the processing unit EU includes a register set comprising individual registers REGA, REGB, and REGC for accommodating specific sections of the machine commands. It is thus possible in the inerpretation phase, in dependence upon the command type, to make available the operands and operand addresses of each machine command using the contents of these registers.

For the monitoring of central processes by the operator, routine programme breaks, and repetitions of machine commands in the event of faulty sequences, it is necessary to be able to identify a machine command which is about to be processed in the processing unit EU.

For this purpose there is provided, as is usual, a command counter P which is designed as a 4 byte register formed by counter flipflops (bistable devices) and bits 8-31 of which contain the effective address of the machine command which is about to be processed. In the event of a consecutive sequence of machine commands and in dependence upon their command format, the address in the command counter P can be incremented by 2, 4, or 6, bytes, or decremented by 2, 4 or 6 for resetting purposes.

There is also provided, connected to and constructed in a similar manner to the command counter P, a further command counter which is referred to here as a preloading command counter PPF. This pre-loading command counter PPF accommodates 3 bytes and contains the effective address with which during command read-out actual access is gained to the working store ASP on the basis of the contents of the address register MA.

The count of this command counter PPF therefore generally exhibits a lead in relation to that of the command counter P; the difference in count can amount to a maximum of 8 bytes i.e. the combined capacity of the two command buffers PF1 and PF2.

On account of the alignment of machine commands to a half word limit or a word limit the contents of the pre-loading command counter PPF can be modified by +2 or +4.

It will be appreciated that because of the differing command lengths and the possibility of word or half word alignment, the commands are not coextensive with store words.

The " effective addresses" refered to above indicate the position in the store of the machine command in question in that the counter P (or, as the case may be, PPF) points to a specific byte of the command in accordance with a predetermined convention.

There is also provided a 3 bit forwards/ backwards counter, referred to here as a leading counter, VLZ whose count indicates the number of half words (i.e. pairs or bytes) of machine commands previously read-out and and intermediately stored in the command buffers PF1 and PF2. Its count is reduced by 1, 2, or 3, in dependence upon the length of each command transferred into he processing unit EU, and is increased by 1 or 2 when a new command word is read-out from the working store ASP.

As it is possible for a programme to modify a machine command in the working store ASP which machine command has already been read-out, it is necessary to monitor such modifications. For this purpose two address comparators AV1 and AV2 are provided which are arranged to compare, in the event of each write-in operation to the working store ASP, the contents of the address register MA with the contents of the pre-loading command counter PPF and the command counter P respectively. If, as a result of this comparison, it is established that write-in access is to be gained in the working store ASP to a machine command already read out and intermediately stored in the command buffers PF1 and PF2, the buffer contents are de dared invalid by setting the count of the leading counter VLZ to zero. The machine commands which have already been read-out are then read-out from the working store ASP in their modified form.

It has already been indicated that the machine commands possess different command formats, but in addition they also differ in respect of the manner in which the command operands are stored. The following Table, in which the abbreviations R, X, I, and S are used to indicate respectively the register address of an operand, the index register address of an operand, a direct operand contained in a command, and the store address of an operand, shows five possible command types RR to SS, related to the relevant store medium for the operands, together with the length in bytes (2 bytes = one half-word) of the command: TABLE

Code Length in Bytes Command Type RR 2 Register-register commands RX 4 Register-store commands with indexing possibility RS 4 Register-store commands SI 4 Store-imme di ate operand commands SS 6 Store-store commands In each machine command the command format is coded in two bit positions of the operations section thereof so that all the requisite path switchings can be derived from this bit combination.

The sequence in the advance loading of machine commands will now be explained making reference to Figs. 2 to 4 which constitute a single flow diagram.

The machine commands are executed in the central processor under the control of microprogrammes, and therefore the advance loading of machine commands is taken into account in the processor structure. The advance loading of a machine command n + i (in this example i < 3) is effetced simultaneously with the provision of addresses and operands of a machine command n which is executed in the processing unit EU, and therefore the control of the advance loading process is included in a micro-programme section which effetcs the aforementioned functions for the machine command n. This ensures that, with a minimal outlay in the central microprogramme control unit, namely with a single additional bit per micro-command, it is possible to overcome the problem of avoiding conflict situations at the interface of the working store ASP as a result of the ad vance loading. Expressed in other words, this means that the flow of the machine command n is not obstructed by the read-out accesses to the working store ASP during the advance loading of the machine command n + i.

In the flow diagram illustrated in Figs. 2 to 4, each individual block corresponds to a respective micro-command. In the flow diagram undivided blocks being to a microprogramme "address and operand provision ", whereas in each block divided by a horizontal broken line the upper half relates to the actual function of a micro-command for a machine command n which is to be executed and the lower half relates to the function to be controlled for the process of the advance loading of a machine command n + i. It is assumed that the processing unit EU includes three general-purpose registers REG1, REG2 and REG3 (not shown in figure 15 for accommodating register operands and baseand index-addresses.

Blocks 1 to 6 of Fig. 2 illustrate the provision of a machine command n in the case of empty or invalid command buffers PF1 and PF2. In the course of a last elementary operation m of the preceding machine command n - 1, it is tested whether the next machine command n which is to be executed has been advance loaded. If so, blocks 1 to 6 are bypassed, but if this test has a negative outcome the command n is read out from the working store ASP, or in the case of a hierarchically classified working store system is read out from the so-called cache thereof.

as indicated by the following elementary operation blocks 1 to 6. In virtual addressing the address of the next machine command n is firstly translated, and then a ' read command ' routine is started as indicated in block 1. This routine is based on the command address contained in the command counter P.

As indicated in block 2, in a second elementary operation the addressed machine command n is read out from the working store ASP and placed in the data register MD, and in a following elementary operation 3 the readout command word is transferred from the data register MD into the command buffers PF1, PF2. This elementary operation closes with a test as to whether the read-out command is located at a half-word limit HWG and is not an RR command. RR commands are the only 2-byte commands, so that only these are completely read-out with one store access even when they lie at a half-word limit. If this test has a negative outcome, blocks 4 to 6 are bypassed, whereas if it has a positive outcome a further analogously executed, readout access to the working store ASP is effected in the elementary operations 4 to 6.

The provision of the machine command n in the command buffers PF, PF2, is then completed, except in the case of an SS command aligned with the word boundary, when the third half-word is read out (as described below) in operations 7 and 14.

Considering firstly only the upper halves of the blocks 7 to 18 Fig. 2 to 4 relating to the micro-programme "address and operand provision", the interpretation phase of the machine command n commences with the elementary operation 7. This command is transferred from the command buffers PF1, PF2 into the processing unit EU, i.e. into the aforesaid registers, of which only the registers referenced REGA to REGC are illustrated in Fig. 1. In this elementary operation, the contents of the general purpose register REG2 are also read-out. Thereafter the micro-programme splits into five branches as schematically illustrated at the bottom of Fig. 2.

Three programme branches for RR commands, RX commands, and RS or SI commands respectively are illustrated in Fig. 3.

In the case of an RR command, in the elementary operation 8, the first register addressed in the command is also read out from the register REG1, and thus in this case both operands of the machine command are made available. In dependence upon the nature of the RR control which is to be executed, immediately thereafter it is possible to branch onto a particular micro-programme for the execution of the called-up machine command. As the actual execution of a machine command is of no interest here, this is merely schematically shown in Fig. 3. By way of example, the elementary operation 9 constitutes a subsequent, arbitrary operation which corresponds to the nature of the calledup machine command n.

In she case of an RS or an SI command, the base address has already been read out from the second register REG2 in elementary operation 7. In the next elementary operation 10 this base address is added to a distance address and simultaneously the first operand is read out from (for RS commands) the general purpose register REG1 or (for SI commands) the command registers. Immediately thereafter a branch is made into a particular micro-programme for the execution of the called-up machine command, as in the case of an RR command, and this is again shown schematically in Fig. 3 by the arbitary operation in block 11.

In the case of an RX command, the base address for the second operand has been readout from the second register REG2 in the elementary operation 7, and in the following elementary operation 12 this base address is added to the distance address, and an index address is read out from the third register REG3. In the following elementary operation 13, the index address is added to the sum of the base and distance addresses and the first operand is read out from the first register REG1. Thereafter a branch is made into the particular micro-programme for the execution of the called-up machine command.

The address and operand provision for SScommands is represented in Fig. 4. As each SS command comprises 3 half-words and the structure of the device for the advance loading is interpreted word-wise, it is necessary to decide whether an SS command which is to be executed is completely contained in the command buffers PF 1 and PF2, in which case no further read-out process is required. This can be determined from the count of the leading counter VLZ; if this count is > 3, the condition is fulfilled, in which case the elementary operation 7, in which the base address for the first store operand has been read out from the second register REG2, is followed by the elementary operation 17. Here, for the first operand, the base address is added to the distance address, and, in parallel, the base address for the second store operand is read out from the third register REG3. In the following elementary operation 18, for the second store operand, the latter base address is added to the distance address. The addresses for both store operands are now established, so that it is possible to branch into the particular micro-programme for the execution of the called up machine command.

If, however, the above-mentioned condition is not fulfilled, i.e. if the leading counter VLZ only possesses a count of 2, the of the 6 bytes of the SS command to be executed only 4 bytes are contained in the command buffers PFl and PF2. Therefore a "read command" process must again be effected. This is carried out in the programme branch shown on the right of Fig. 4. In this case in the elementary operation 7 the first 4 bytes of the SS command have been transferred into the processing unit EU and at the same time the base address of the first store operand has been read out from the second register REG2.

In the lower half of this elementary operation illustrated in Fig. 2, in parallel, a "read command " process is started, and this is preceded by an address translation if virtual addressing is being used. Now in the next elementary operation 14 of the address of the first store operand is made available by adding the base address read-out from the second register REG2 to the distance address, as indicated in the upper half of block 14, and at the same time, i.e. in parallel therewith, as indicated in the lower half of block 14, the second part of the SS command is read out from the working store ASP to the data register MD. In the next elementary operation 15 the read-out command word is transferred into the second command buffer PF2, and the last 2 bytes of the SS command are trans ferred into the processing unit EU. In the processing unit EU. In the following elementary operation 16 of the base address of the second store operand is read out from the third register REG3, and in the subsequent elementary operation 18 this base address is added to the distance address so that the address for the second store operand is made available.

As explained above, the micro-programme address and operand provision" only re- quires a working store cycle for the machine command n in the event that an SS command is not contained in full in the command buffers PF1 and PF2. In all five micro-programme branches it is possible to accommodate command read-out accesses for the next machine command(s) n + i. A store access for the advance loading of a machine command n + employs three consecutive elementary operations.

The sequence for the advance loading of a machine command n + i is identical for the micro-programme branches RR, RX, RS/SI, and SS. ( < VLZ > ) 3). In these cases it commences in elementary operation 7 and ends with the particular next but one elementary operation 9, 11, 13, and 18 respectively. In the case of an SS command an a count of the leading counter of 2, the advance loading of the next command does not commence until elementary operation 15 and ends with the next but one elementary operation 18.

In the first elementary operation for the advance loading (elementary operation 7 or 15) the virtual command address for the machine command n + i is taken from the advance loading command counter PPF. In the virtual addressing, this command address is, in the same elementary operation, translated into a real address of the working store ASP and the process "read-out command word" is started. In the next elementary operation 8, 10, 1;, or 16 the command word addressed in this way is read out from the working store ASP, and in the final elementary operation 9, 11, 13 or 18 the read-out command is transferred into the command buffers PF1, PF2.

Thus in most cases, following the execution of the machine command n, at least the next machine command n + 1 which is to be executed is always contained in the command buffers PF1 and PF2. If, by exception, these conunand buffers are empty, or their contents are declared invalid, this is recognised in the last elementary operation m of the machine command n, in that the count of the leading counter VLZ is analysed. Only then is it necessary to utilise the micro-programme component "command provision" with the elementary operations 1 to 3 or 1 to 6.

This situation can occur-when the machine commands of a sequence of machine commands which are to be executed are not con tained consecutively in the working store; this applies e.g. in the case of fulfilled jump commands or programme breaks. As the com mand counter P renders the particular machine commands which are to be executed identi fiable, any discontinuous modifications in the command counter which thus occur can be analysed.

Furthrmore, during its execution, a machine command n may modify consecutive machine commands n + 1 to n t- 3 in the work ing store ASP. Such modifications of commands already read-out by the advance loading described above are recognised with the aid of the address comparators AV1 and AV2.

Finally in the event of a "read-out command" programme, hardware-address transation errors or store access errors can occur.

Such errors are handled in operating systems of modern data processing systems by fault routines into which the resetting of the leading counter VLZ can also be incorporated.

Thus in all these cases, machine commands having been read-out by advance loading are suppressed by the resetting of the leading counter VLZ. In the last-mentioned machine fault treatment this is necessary in order to maintain a clearly defined assignment of the occurred error to the machine command and thus for example to facilitate its automatic repetition.

WHAT WE CLAIM IS: 1. A data processing system comprising a processing unit arranged in operation to execute machine commands under microprogramme control, a store which serves to store the machine commands, a data register having a data width of one store word, an address register for addresing the store with a store address to write in thereto from and to read out therefrom to the data regis

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. ferred into the processing unit EU. In the processing unit EU. In the following elementary operation 16 of the base address of the second store operand is read out from the third register REG3, and in the subsequent elementary operation 18 this base address is added to the distance address so that the address for the second store operand is made available. As explained above, the micro-programme address and operand provision" only re- quires a working store cycle for the machine command n in the event that an SS command is not contained in full in the command buffers PF1 and PF2. In all five micro-programme branches it is possible to accommodate command read-out accesses for the next machine command(s) n + i. A store access for the advance loading of a machine command n + employs three consecutive elementary operations. The sequence for the advance loading of a machine command n + i is identical for the micro-programme branches RR, RX, RS/SI, and SS. ( < VLZ > ) 3). In these cases it commences in elementary operation 7 and ends with the particular next but one elementary operation 9, 11, 13, and 18 respectively. In the case of an SS command an a count of the leading counter of 2, the advance loading of the next command does not commence until elementary operation 15 and ends with the next but one elementary operation 18. In the first elementary operation for the advance loading (elementary operation 7 or 15) the virtual command address for the machine command n + i is taken from the advance loading command counter PPF. In the virtual addressing, this command address is, in the same elementary operation, translated into a real address of the working store ASP and the process "read-out command word" is started. In the next elementary operation 8, 10, 1;, or 16 the command word addressed in this way is read out from the working store ASP, and in the final elementary operation 9, 11, 13 or 18 the read-out command is transferred into the command buffers PF1, PF2. Thus in most cases, following the execution of the machine command n, at least the next machine command n + 1 which is to be executed is always contained in the command buffers PF1 and PF2. If, by exception, these conunand buffers are empty, or their contents are declared invalid, this is recognised in the last elementary operation m of the machine command n, in that the count of the leading counter VLZ is analysed. Only then is it necessary to utilise the micro-programme component "command provision" with the elementary operations 1 to 3 or 1 to 6. This situation can occur-when the machine commands of a sequence of machine commands which are to be executed are not con tained consecutively in the working store; this applies e.g. in the case of fulfilled jump commands or programme breaks. As the com mand counter P renders the particular machine commands which are to be executed identi fiable, any discontinuous modifications in the command counter which thus occur can be analysed. Furthrmore, during its execution, a machine command n may modify consecutive machine commands n + 1 to n t- 3 in the work ing store ASP. Such modifications of commands already read-out by the advance loading described above are recognised with the aid of the address comparators AV1 and AV2. Finally in the event of a "read-out command" programme, hardware-address transation errors or store access errors can occur. Such errors are handled in operating systems of modern data processing systems by fault routines into which the resetting of the leading counter VLZ can also be incorporated. Thus in all these cases, machine commands having been read-out by advance loading are suppressed by the resetting of the leading counter VLZ. In the last-mentioned machine fault treatment this is necessary in order to maintain a clearly defined assignment of the occurred error to the machine command and thus for example to facilitate its automatic repetition. WHAT WE CLAIM IS:

1. A data processing system comprising a processing unit arranged in operation to execute machine commands under microprogramme control, a store which serves to store the machine commands, a data register having a data width of one store word, an address register for addresing the store with a store address to write in thereto from and to read out therefrom to the data register in each case one store word, two command buffers each having the same data width as the data register and into which store words can be transferred from the data register, means arranged in operation to supply machine commands previously read out from the store selectively from the command buffers to the processing unit to be executed thereby, a first command counter which is arranged to con tain an address indicative of the position in the store of the machine command which is about to be executed in the processing unit, a second command counter which is arranged to con tain an address indicative of the position in the store of the latest machine command to be read out from the store, whereby a machine command is read out from the store and stored in the command buffers during the execution in the processing unit of a previous machine command, and comparator means arranged in operation during each write-in access to the store to compare the store address contained in the address register with

the addresses contained in the command counters and to indicate whenever such a store access takes place in respect of store locations corresponding to commands already read out but still awaiting execution.

2. A system as claimed in claim 1, wherein the command buffers comprise a first register into which commands are transferred directly from the data register and a second register into which commands are transferred from the first register and the means for supplying machine commands to the processing unit comprises a first switch having a data width of one store word and second switch having a data width of half of one store word, wherein for the processing of machine commands which can be of one, two or three half-words in length, the first switch is arranged to switch through to the processing unit selectively any one of the contents of the data register, the contents of the second command buffer, and the contents of half of the second command buffer assigned to relatively lower order bits together with the contents of half of the first command buffer assigned to relatively higher order bits and the second switch is arranged to switch through to the processing unit selectively the contents of either of the two halves of the first command buffer.

3. A system as claimed in claim 1 or claim 2, wherein the processing unit includes a register set comprising individual registers into which the machine commands are selectively transferred.

4. A system as claimed in any of claims 1 to 3, wherein consecutive elementary operations of a micro-programme routine "read-out command" for making available a machine command are effected concurrently with consecutively executed elementary operations, which require no store access, of a microprogramme routine " provision of addresses and operands" for the provision of addresses and operands of a previous machine command which is to be executed.

5. A system as claimed in any of claims 1 to 4 and including a forwards/backwards counter whose count is arranged to be in teased or decreased by a corresponding amount whenever a command word is transferred to or from the command buffer and to be reset whenever said comparator indicates the occurrence of a write-in store access in respect of store locations corresponding to commands already read-out but still awaiting execution, whereby its count corresponds to the number of halves of store words validly intermediately stored in the command buffers.

6. A system as claimed in claim 5 including means arranged in operation to reset the count of the forwards/backwards counter in the event of each discontinuous change in the address contained in the first command counter.

7. A system as claimed in claim 5 or 6, wherein the count of the forwards/backwards counter is reset during a fault treatment routine which is triggered in the event of a fault.

8. A system as claimed in claim 5, 6 or 7 when dependent on claim 4, wherein during the final micro-command in the execution of each machine command the count of the forwards/backwards counter is evaluated to test whether the following machine command is already intermediately stored in the command buffers, and wherein if this is the case immediately thereafter the micre-programme routine " provision of addresses and operands" for the execution of said following machine command is started and otherwise a micro programme routine is run to read out said following machine command from the store.

9. A micro-programme controlled data pro cessing system substantially as herein described with reference to the accompanying drawings.