GB1537419A - Digital information storage device - Google Patents
Digital information storage deviceInfo
- Publication number
- GB1537419A GB1537419A GB2642677A GB2642677A GB1537419A GB 1537419 A GB1537419 A GB 1537419A GB 2642677 A GB2642677 A GB 2642677A GB 2642677 A GB2642677 A GB 2642677A GB 1537419 A GB1537419 A GB 1537419A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memories
- counter
- address
- memory
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
1537419 Memory system V F GUSEV G N IVANOV I KRENGEL M Z SHAGIVALEEV A U YARMUKHAMETOV V Y KONTAREV J I SCHETININ and V Y KREMLEV 23 June 1977 [7 July 1976] 26426/77 Heading G4A A switch 20 selectively provides to the address input of a memory 2 the outputs of counters 17, 23, the output of counter 17 also being supplied to the address input of a memory 1, the two memories 1, 2 receiving data from a bus 8 and supplying respective outputs to buses 13, 14 via gates 11, 12 controlled by a control unit 5 connected to the output of a clock pulse oscillator 27. Data may be written into identical addresses, supplied by counter 17, in the two memories 1, 2. If two operands are to be added the addresses of the two operands are supplied to counters 17, 23 which address the memories 1, 2 respectively during the first half of the operation cycle, the result being written in both memories 1, 2, at the address of the first operand as specified by counter 17, in the second half of the operation cycle. An operand may be read from an address in memory 2 specified by counter 23 and re-written in both memories 1, 2 at an address specified by counter 17.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SU762379700A SU613402A1 (en) | 1976-07-07 | 1976-07-07 | Storage |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1537419A true GB1537419A (en) | 1978-12-29 |
Family
ID=20668233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2642677A Expired GB1537419A (en) | 1976-07-07 | 1977-06-23 | Digital information storage device |
Country Status (10)
Country | Link |
---|---|
JP (1) | JPS5317036A (en) |
BG (1) | BG29547A1 (en) |
DD (1) | DD132695A1 (en) |
DE (1) | DE2730794A1 (en) |
FR (1) | FR2357979A1 (en) |
GB (1) | GB1537419A (en) |
IN (1) | IN147070B (en) |
PL (1) | PL109526B1 (en) |
RO (1) | RO75686A (en) |
SU (1) | SU613402A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3070394D1 (en) * | 1980-11-26 | 1985-05-02 | Ibm Deutschland | Multiple-address highly integrated semi-conductor memory |
US5436863A (en) * | 1993-04-26 | 1995-07-25 | Nec Corporation | Semiconductor memory device |
EP0713221B1 (en) * | 1994-11-18 | 2002-01-09 | STMicroelectronics S.r.l. | Synchronization device for output stages, particularly for electronic memories |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3651476A (en) * | 1970-04-16 | 1972-03-21 | Ibm | Processor with improved controls for selecting an operand from a local storage unit, an alu output register or both |
US3737866A (en) * | 1971-07-27 | 1973-06-05 | Data General Corp | Data storage and retrieval system |
-
1976
- 1976-07-07 SU SU762379700A patent/SU613402A1/en active
-
1977
- 1977-06-10 IN IN865/CAL/77A patent/IN147070B/en unknown
- 1977-06-23 GB GB2642677A patent/GB1537419A/en not_active Expired
- 1977-07-04 RO RO7790919A patent/RO75686A/en unknown
- 1977-07-04 PL PL19936877A patent/PL109526B1/en unknown
- 1977-07-05 DD DD19989077A patent/DD132695A1/en unknown
- 1977-07-05 FR FR7720656A patent/FR2357979A1/en active Granted
- 1977-07-07 BG BG7736829A patent/BG29547A1/en unknown
- 1977-07-07 JP JP8049477A patent/JPS5317036A/en active Pending
- 1977-07-07 DE DE19772730794 patent/DE2730794A1/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
FR2357979A1 (en) | 1978-02-03 |
FR2357979B1 (en) | 1981-11-27 |
SU613402A1 (en) | 1978-06-30 |
PL109526B1 (en) | 1980-06-30 |
DE2730794A1 (en) | 1978-01-19 |
RO75686A (en) | 1981-02-28 |
IN147070B (en) | 1979-11-03 |
BG29547A1 (en) | 1980-12-12 |
PL199368A1 (en) | 1978-02-13 |
DD132695A1 (en) | 1978-10-18 |
JPS5317036A (en) | 1978-02-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |