GB1517926A - Electronic stores - Google Patents

Abstract

1517926 FET storage matrix SIEMENS AG 9 Sept 1975 [20 Sept 1974 12 Feb 1975] 36980/75 Heading H1K [Also in Division G4] In an electronic store consisting of a matrix of storage cells, each consisting solely of an N- channel storage FET with a floating gate and a superposed control gate both of which control the main current path of the FET and so constructed as to permit programming by negative charging the floating gate by channel injection, at least some of the corresponding terminals, e.g. sources, drains or channel of at least some of the cells are connected together. In the embodiment, Fig. 2, the control gates of all cells in a row are connected to the respective X-conductor, the drains of all cells in a column to the respective Y-conductor, and the sources of all cells in the matrix to a common point S o , which may be earthed by connection to S U , placed at voltage U by connection to R U , or left floating. The cells may be formed on a common semiconductor substrate which may be earthed or left floating and may also include the control circuitry S t though the store and control circuitry may alternatively be in separate epitaxial semiconductor layers on a common substrate of spinel or sapphire. The construction enables voltages to be applied to programme the cell individually by storing electrons on their floating gates and to read the state of individual cells. Stored information may be erased from individual cells, or from all cells in a row or the matrix simultaneously. Such simultaneous erasure can be achieved with minimal heat generation if the FETs are of the enhancement type, by using the Fowler- Nordheim tunnelling or, if the floating gates are of P-doped polycrystalline silicon more than 1000 Š thick, by the gate surface effect mechanism. The tunnelling mechanism requires application of a direct voltage or series of pulses between control gate and source, drain or channel region with the others of these regions floating, while the gate surface effect requires a train of pulses with steep leading flanks, e.g. with a frequency of 100 KHz to 1 MHz and a keying ratio of 1 : 1. In either case voltage pulses are applied with the control gate held at a fixed potential, such as earth. The thickness of insulation between the floating gate and substrate is so chosen e.g. at 600 Š to avoid partial discharge of a cell by drain avalanching when its drain is connected in common with that of another cell being programmed, and to prevent avalanche effect at a reverse-biased PN junction in the main current path of the FET making a major contribution to erasure of the cell. Lower operating voltages can be used if the capacity between the control and floating gates greatly exceeds that between the floating gate and substrate, and contamination of the gate insulation of the gate insulation, reduced by so operating that the programming and erasure currents pass through spaced portions of it.