GB1498498A - Frame aligners for time division multiplex(tdm)communication systems - Google Patents

Abstract

1498498 TDM Frame aligner PLESSEY CO Ltd 10 Feb 1976 [5 March 1975] 9041/75 Heading H4M The frame aligners at each exchange or switching centre of a multi-exchange network in a time division communication system provide basic dynamic compensation for varying frame phase and in addition optimize the initial/remote frame phase relationship and ensure that any information loss occurs only at insignificant instants, such as switch-on or during frame synchronization recovery. An aligner at a second exchange receiving a data bit system transmitted over a highway from a first exchange under the control of the first exchange clock includes a multi address buffer store RAM and an address selector ASEL for addressing the buffer store twice in each bit period of a TDM frame of the second exchange. The addresses are selected from a first write counter WC driven at a bit rate equivalent to that of the data bit stream and a second read counter driven at the rate of the clock system at the second exchange. Upon successive detection by an overlap detector (gates G7 &c.) of a count differential N between the counts of the first and second counters, where N is the maximum number of bits drift expected between the two systems, a delay device DL is alternatively inserted into and removed from a data path from the buffer store. When the delay device is inserted the second counter is advanced by a number equivalent to the number of stages in the delay device, and when the delay is removed the second counter is preset to align with the first t.d.m. multiplex frame of the second exchange when frame synchronization is recovered. Incoming data received at IH in pseudo ternary bipolar form is converted at BBC to bipolar non return to zero form. The clock of the input data is extracted at CE and applied as an input BRC to the write counter WC and to a bit aligner CC. The counter WC enables the input data channel to be monitored (e.g. counts 0-7#channel 0, counts 248-255#channel 31) and when channel 0, the synchronizing channel, is determined to be present, the gate G3 feeds a signal to the sync. pattern detector SPDS, which compares the received sync. pattern with a stored pattern. If an out of sync. condition is found, a toggle TG3 causes a signal DD to be delivered to an output gate G17 to prevent any data leaving the aligner, and the detector SPDS conducts a search until sync. is established. The input data is fed to the buffer memory RAM under the control of the write counter WC, via the address selector ASEL and read out by reference to the read counter which counts bits from the local or station clock. This should be at least two channels later to avoid the possibility of overlap. Channel 31, bit 8 in the read counter causes gate G1 to deliver a signal to the gate G7, and any count in the write counter corresponding to channel 31, bits 1-8 or channel 0 bits 1-8 causes gate G9 to deliver an enable sign to the gate G7. This gives an output when the coincidence between the signals from G 14 and G9 is obtained to set the toggle TG2 and disable the gate G 13 which usually enables data signals to pass directly on reading from the buffer RAM to the aligner output. The gate G11 is enabled and data passes via the 16 bit delay DL to the output. The toggle signal also causes an advance signal to be delivered to the read counter RC. When the separation between write and read becomes more than 16 bits (two channels), the toggle is reset and data proceeds directly to the output.