GB1497210A - Matrix memory - Google Patents

Abstract

1497210 Variable threshold FET memory; read out NCR CORP 5 May 1976 [13 May 1975] 18427/76 Heading G4C [Also in Division H3T] Binary data is read from a matrix array of variable threshold storage FETS by comparing the signal from a selected storage FET with that from a variable threshold reference FET set to a predetermined one of the two binary threshold values. As shown a matrix array of MNOS storage FETS 20 has one MNOS reference FET 42, 44 per row, although it is stated that a single reference FET for the whole 'matrix could be used. The whole circuit may be formed as an integrated circuit. The comparison used on read out compensates for variations in transistor parameters. A storage FET, say 20a, is selected by decoder 32 energizing a row drive transistor 34a to connect an enabling voltage to the appropriate row, and by decoder 22 energizing a column select transistor, 28a, to connect a constant current source 52, Fig. 2 (not shown), to the appropriate column. Constant current source 52 drives a constant current through the column select transistor, the storage transistor 20a, and a conductive power supply transistor 30a. Depending on its threshold value the storage transistor 20a present a high or low impedance so that the voltage at the output of the column select transistor and the output of the constant current source, which acts independently of voltage, reflects the threshold value and hence the stored datum. Simultaneously with the selection of a storage FET the corresponding reference FET 42 is selected and is driven by an identical constant current source 54. The two voltage signals are connected to the two inputs of a bistable 50, except that the reference voltage is offset by circuit 56 so as to lie between the two voltages corresponding to the two threshold values obtained from a storage FET. The polarity of the voltage across the bistable 50 thus indicates the stored datum and sets the bistable accordingly. The constant current source Fig. 2 (not shown), includes two FETS, one of high and the other of low impedance, connected in series between power supply lines to provide a bias voltage to saturate a further FET which is connected to one of the power lines to provide a constant current independent of output voltage.