GB1494677A - Digital monitoring circuits - Google Patents

Abstract

1494677 Transistor pulse circuits; APC systems SIEMENS AG 26 Feb 1975 [18 March 1974] 7986/75 Headings H3T and H3A A pulse width comparator for monitoring the exceedance of the upper, lower limits of a phase lock loop pull-in range represented by first and second instants in a loop input reference pulse comprises a first monostable multivibrator MM1 triggered by a reference pulse I st and providing an output pulse of width equal to the duration between the front flank of the pulse I st and the first instant in the same pulse, a second monostable multivibrator triggered by the loop phase discriminator output to provide a pulse of width equal to the duration between the second instant and the trailing flank of I st , and gating circuitry including an inverter A, AND gates B, C, OR gate D for triggering a switching element SG via a set-reset bistable circuit E, F. The trailing flanks of the reference and discriminator output pulses are arranged to coincide (Fig. 1, not shown) and the comparator monitors whether the discriminator pulse width is large for its front flank to precede the first instant or small for its front flank to succeed the second instant. In either case, an SR bi-stable circuit is set via one of AND gates B, C and OR gate D for triggering an alarm via a switching element SG.