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GB1485183A - Integrated circuit devices and their fabrication - Google Patents

Integrated circuit devices and their fabrication

Info

Publication number
GB1485183A
GB1485183A GB103175A GB103175A GB1485183A GB 1485183 A GB1485183 A GB 1485183A GB 103175 A GB103175 A GB 103175A GB 103175 A GB103175 A GB 103175A GB 1485183 A GB1485183 A GB 1485183A
Authority
GB
United Kingdom
Prior art keywords
level
metallization
dielectric mask
semi
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB103175A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of GB1485183A publication Critical patent/GB1485183A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

1485183 Semi-conductor devices WESTERN ELECTRIC CO Inc 10 Jan 1975 [14 Jan 1974] 1031/75 Heading H1K In the manufacture of an integrated circuit a mesa portion of a semi-conductor body is laterally isolated by inset oxide 16a, 166, 16c, a first patterned metallization level 17, 18, 19 is provided having parts which overlap the inset oxide 16 and the isolated portion 14, an apertured dielectric mask 20a, 20b, 20c is deposited over the surface and impurities are introduced into a region 21 of the isolated portion defined by a masking layer constituted by the combination of the first level metallization 17-19, the inset oxide 16 and the dielectric mask 20. Preferably a second patterned level of metallization is subsequently deposited on the dielectric mask 20 to contact the region 21 and areas of the first metallization level exposed through other openings in the mask 20. In the manufacture of an integrated circuit containing an NPN transistor the semi-conductor body comprises a P-type B doped Si substrate 11 having an N+ As or Sb diffused surface zone 13 which is buried beneath a P- type epitaxial layer. Inset oxide 16a, 16b, 16c is formed by selective anisotropic etching followed by oxidation, to laterally isolate portions 14, 15 of the epitaxial layer as shown. The portion 15 is converted to N+-type conductivity by diffusion or ion implantation of P. The first metallization level 17, 18, 19, e.g. of Al, Au, Si or W, is applied and selectively covered with the dielectric mask 20, which may be a silicon nitride-silicon oxide composite. The N+-type emitter region 21 is formed by As diffusion or ion implantation followed by a low temperature anneal and finally, a second metallization level is formed, contacting the emitter region 21 and exposed areas 17, 19 of the first level.
GB103175A 1974-01-14 1975-01-10 Integrated circuit devices and their fabrication Expired GB1485183A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US43289674A 1974-01-14 1974-01-14

Publications (1)

Publication Number Publication Date
GB1485183A true GB1485183A (en) 1977-09-08

Family

ID=23718017

Family Applications (1)

Application Number Title Priority Date Filing Date
GB103175A Expired GB1485183A (en) 1974-01-14 1975-01-10 Integrated circuit devices and their fabrication

Country Status (7)

Country Link
JP (1) JPS50104579A (en)
CA (1) CA1010157A (en)
DE (1) DE2500867A1 (en)
FR (1) FR2258001B1 (en)
GB (1) GB1485183A (en)
IT (1) IT1028309B (en)
NL (1) NL7500360A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2605641C3 (en) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen High frequency transistor and process for its manufacture
FR2470444A1 (en) * 1979-11-21 1981-05-29 Radiotechnique Compelec Electrical connection network on semiconductor base mfg. method - using floating conductors isolated from base and formed by localised anodic oxidation of metallic coating

Also Published As

Publication number Publication date
JPS50104579A (en) 1975-08-18
FR2258001A1 (en) 1975-08-08
DE2500867A1 (en) 1975-07-24
CA1010157A (en) 1977-05-10
NL7500360A (en) 1975-07-16
IT1028309B (en) 1979-01-30
FR2258001B1 (en) 1978-08-25

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee