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GB1473730A - Method and apparatus for the control of the transmission of data exchanged between a computer and one or more peripherals - Google Patents

Method and apparatus for the control of the transmission of data exchanged between a computer and one or more peripherals

Info

Publication number
GB1473730A
GB1473730A GB3524674A GB3524674A GB1473730A GB 1473730 A GB1473730 A GB 1473730A GB 3524674 A GB3524674 A GB 3524674A GB 3524674 A GB3524674 A GB 3524674A GB 1473730 A GB1473730 A GB 1473730A
Authority
GB
United Kingdom
Prior art keywords
signal
data
lapse
lapses
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3524674A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CII HONEYWELL BULL
Original Assignee
CII HONEYWELL BULL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CII HONEYWELL BULL filed Critical CII HONEYWELL BULL
Publication of GB1473730A publication Critical patent/GB1473730A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Communication Control (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)

Abstract

1473730 Digital data transmission COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII HONEYWELL BULL 9 Aug 1974 [3 Sept 1973] 35246/74 Heading G4A In data transmission between a computer 1 (Fig. 7) and a peripheral 2, in which a first signal represents the address at which data is to be read from or written into and a second signal represents the data, both signals are checked for errors. As described the computer and peripheral are connected by two circuits 3, 4. Initially circuit 3 sends a signal ENO and CSO to circuit 4, signal CSO being an outward check signal which results in circuit 4 sending an inward check signal CSI to unit 3. After validation of address data on line DP gate 5 is enabled and first the signal CSO and then a signal CSI lapse. To transfer data to the peripheral, circuit 3 sends a signal DSO which results in a return signal DSI at which signal DSO lapses and the data being transmitted is validated after which signal DSI lapses. This recults in signal ENI being generated which allows signal ENO to lapse. To read-out data to the computer when the signal CSI lapses, signal ENI is generated which makes a signal ENO lapse generating signal DSI. This results in signal DSO being generated, signal DSI then lapsing to validate gate 5 so that the data is checked after which signal DSO lapses causing signal ENI to lapse. If an error is detected in the address or data an error signal EV3 and signal ENI are generated, the latter starting a sequence of signals which results in signal ENO being allowed to lapse and then regenerated to start a new cycle.
GB3524674A 1973-09-03 1974-08-09 Method and apparatus for the control of the transmission of data exchanged between a computer and one or more peripherals Expired GB1473730A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7331760A FR2242910A5 (en) 1973-09-03 1973-09-03

Publications (1)

Publication Number Publication Date
GB1473730A true GB1473730A (en) 1977-05-18

Family

ID=9124560

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3524674A Expired GB1473730A (en) 1973-09-03 1974-08-09 Method and apparatus for the control of the transmission of data exchanged between a computer and one or more peripherals

Country Status (8)

Country Link
US (1) US3909782A (en)
JP (1) JPS581447B2 (en)
BR (1) BR7407309D0 (en)
DE (1) DE2442013A1 (en)
ES (1) ES429538A1 (en)
FR (1) FR2242910A5 (en)
GB (1) GB1473730A (en)
IT (1) IT1020375B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1046598B (en) * 1974-05-16 1980-07-31 Honeywell Inf Systems INTERFACE FOR CONNECTION OF PERIPHERAL EQUIPMENT TO A COMPUTER PROVIDED WITH SIGNALING AND DISTINCTION MECHANISMS TRANSLATING TYPES OF ERROR
US4335426A (en) * 1980-03-10 1982-06-15 International Business Machines Corporation Remote processor initialization in a multi-station peer-to-peer intercommunication system
GB2075802B (en) * 1980-05-12 1984-05-31 Control Data Corp Network access device
US4458312A (en) * 1981-11-10 1984-07-03 International Business Machines Corporation Rapid instruction redirection
US4567595A (en) * 1983-03-31 1986-01-28 At&T Bell Laboratories Multiline error detection circuit
US4535421A (en) * 1983-07-05 1985-08-13 Pitney Bowes Inc. Universal real time transparent asynchronous serial/echoplex converter
US4594713A (en) * 1983-12-22 1986-06-10 Gte Automatic Electric Inc. Remote data link receive data reformatter
US4598404A (en) * 1983-12-22 1986-07-01 Gte Automatic Electric Inc. Data format arrangement for communication between the peripheral processors of a telecommunications switching network
JPH0670787B2 (en) * 1984-06-29 1994-09-07 富士通株式会社 Command transfer control system between processors
WO1991013780A1 (en) * 1990-03-06 1991-09-19 Siemens Aktiengesellschaft Control system for a vehicule drive

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303476A (en) * 1964-04-06 1967-02-07 Ibm Input/output control
US3579200A (en) * 1969-07-30 1971-05-18 Ibm Data processing system
DE2131787C3 (en) * 1971-06-26 1973-12-20 Ibm Deutschland Gmbh, 7000 Stuttgart Circuit arrangement for error detection in data processing systems
US3721961A (en) * 1971-08-11 1973-03-20 Ibm Data processing subsystems

Also Published As

Publication number Publication date
ES429538A1 (en) 1976-09-01
US3909782A (en) 1975-09-30
BR7407309D0 (en) 1975-09-09
JPS581447B2 (en) 1983-01-11
IT1020375B (en) 1977-12-20
JPS5056134A (en) 1975-05-16
DE2442013A1 (en) 1975-03-13
FR2242910A5 (en) 1975-03-28

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PE20 Patent expired after termination of 20 years

Effective date: 19940808