GB1460698A - Time division switch - Google Patents
Time division switchInfo
- Publication number
- GB1460698A GB1460698A GB1116875A GB1116875A GB1460698A GB 1460698 A GB1460698 A GB 1460698A GB 1116875 A GB1116875 A GB 1116875A GB 1116875 A GB1116875 A GB 1116875A GB 1460698 A GB1460698 A GB 1460698A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bit
- superhighway
- highways
- delay
- incoming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/06—Time-space-time switching
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
1460698 Automatic exchange systems; multiplexing INTERNATIONAL STANDARD ELECTRIC CORP 18 March 1975 [22 March 1974] 11168/75 Headings H4K and H4M In a TDM system wherein information is switched between a pair of parallel super highways mpe, mps using a store MC for each time slot on the incoming super highway mpe, means M, DM are provided for multiplexing and demultiplexing a plurality of serial bit highways mse1-mse8, mss1-mss8 onto and off the superhighways and for simultaneously performing a serial to parallel or parallel to serial conversion. Fig. 2 shows the multiplexer/serial to paralle converter M for multiplexing eight, eight bit per channel 32 channel serial highways mse1-mse8 on to a single 256 channel, eight bit per channel parallel superhighway mpe. The arrangement comprises an 8 x 8 switching matrix MCE and a plurality of delay buffers cd each applying a delay of one bit length. By inserting a delay of x-1 bit lengths into the xth incoming highway msex, and a delay of 8-x bit lengths into the wire of the xth bit position of superhighway mpe, the eight input wires msed1-msed8 can be simultaneously switched to corresponding ones of the output wires mped1-mped8 during the length of each bit position, so as to provide the 256 channel parallel superhighway, thetotal delay for each bit through the multiplexer being one time slot of the incoming 32 slot highways. Figs. 3-6 (not shown) illustrate the above operation for the transfer of one time slot of an incoming highway. The demultiplexer DM uses the above arrangement in reverse. It is said that both the multiplexer and demultiplexer can be realised using a plurality of the shift switching matrices disclosed in Specification 1,415,919. The time switch MC for switching between super highways comprises a 256 position store into which the information on the incoming superhighway is written sequentially, the information being read out under the control of a connection store MTS in the appropriate time slots of the outgoing superhighway, to provide a non-blocking switch.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7409802A FR2265240B1 (en) | 1974-03-22 | 1974-03-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1460698A true GB1460698A (en) | 1977-01-06 |
Family
ID=9136697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1116875A Expired GB1460698A (en) | 1974-03-22 | 1975-03-18 | Time division switch |
Country Status (5)
Country | Link |
---|---|
AU (1) | AU7894075A (en) |
BE (1) | BE827042R (en) |
DE (1) | DE2512047A1 (en) |
FR (1) | FR2265240B1 (en) |
GB (1) | GB1460698A (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2359562A1 (en) * | 1976-07-20 | 1978-02-17 | Labo Cent Telecommunicat | DIGITAL SYSTEM TRANSPOSITION DEVICE |
FR2376572A1 (en) * | 1976-12-30 | 1978-07-28 | Roche Alain | SERIAL-PARALLEL CONVERSION AND MULTIPLEXING OR PARALLE-SERIAL CONVERSION AND DEMULTIPLEXING CIRCUITS FOR DIGITAL MULTIPLEXES |
US4143241A (en) * | 1977-06-10 | 1979-03-06 | Bell Telephone Laboratories, Incorporated | Small digital time division switching arrangement |
FR2454243A1 (en) * | 1979-04-12 | 1980-11-07 | Roche Alain | TDM switching network with two time division stages - has buffer stores controlled to transfer a word in particular incoming slot to particular outgoing highway |
IT1149253B (en) * | 1980-09-09 | 1986-12-03 | Sits Soc It Telecom Siemens | SWITCHING NETWORK FOR PCM CHANNELS |
DE3230054A1 (en) * | 1982-08-12 | 1984-02-16 | Siemens Ag | DEMULTIPLEXER |
CA2100729C (en) * | 1993-07-16 | 2001-01-16 | Simon Skierszkan | Serial bit rate converter embedded in a switching matrix |
-
1974
- 1974-03-22 FR FR7409802A patent/FR2265240B1/fr not_active Expired
-
1975
- 1975-03-10 AU AU78940/75A patent/AU7894075A/en not_active Expired
- 1975-03-18 GB GB1116875A patent/GB1460698A/en not_active Expired
- 1975-03-19 DE DE19752512047 patent/DE2512047A1/en not_active Withdrawn
- 1975-03-24 BE BE2054223A patent/BE827042R/en active
Also Published As
Publication number | Publication date |
---|---|
FR2265240A1 (en) | 1975-10-17 |
AU7894075A (en) | 1976-09-16 |
DE2512047A1 (en) | 1975-10-02 |
FR2265240B1 (en) | 1977-09-30 |
BE827042R (en) | 1975-09-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
746 | Register noted 'licences of right' (sect. 46/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |