GB1457260A - Expandable function electronic calculator - Google Patents

Abstract

1457260 Calculators TEXAS INSTRUMENTS Inc 14 Dec 1973 [16 May 1973] 58043/73 Heading G4A An electronic calculator includes a first chip 5 (Fig. 2a) including data registers and an arithmetic and logic unit and receiving inputs from a keyboard unit and supplying output signals to a display unit and a second chip 6 having a read only memory storing instructions for controlling operations on the first chip, the first chip providing a synchronizing signal to the other chip. The calculator is of the desk top type with additional chips e.g. for storage, an output display being provided by a NIXIE tube, a liquid crystal unit or light emitter diodes. A printed read-out using a thermal or drum printer may be provided. Data and read only memory chips.-State (S) times from push-pull matrix 280 (Fig. 2b1) provide the timing control for the data chip, there being 16 state times in one display (D) time. The arithmetic unit on the data chip is of the bit parallel, digit serial type, the type of operation performed being determined by the instruction read out from the read only memory in response to e.g. operation of a key. It operates as though the data were binary, a correcter matrix converting the data back to binary coded decimal. The storage on the data chip is a memory 23 (addressed sequentially by the S signals), comprising a plurality of registers storing data in MOS transistor cells, each column of cells being refreshed at its associated S time. On the readonly memory chip, program counter 25 (Fig. 2c) which stores 11 address bits (4 zeros being added) addresses the read-only memory to generate a 13 bit instruction word I 0 -I 12 , part of which is fed via register 581 and pins IRGA, IRGB to the data chip, where it is clocked into control decoder 212 (Fig. 2b4). Decode matrices decode the information to provide signals to control the transfer of data amongst registers in memory 23 and into and out of the arithmetic unit via selector gates (Fig. 2b1, 2b2) and to provide mask information to allow manipulation on part e.g. the mantissa of a selected word. If the entered information is data it is entered via lines 410 (Fig. 2b4) and the arithmetic unit into A register in the memory 23. Data for display is transferred from this register to pins A1-A8 together with comma and decimal point information. Control signals CONA, CONB from the data chip indicate to external chips when instructions are to be entered and executed, CONA providing a hold instruction and CONB when high representing an idle condition. A COND signal results in a conditional branch instruction if for example a particular flag is set and so sets a circuit 261. This circuit may also be set by a busy signal from e.g. the printer chip if it is active and cannot receive any more data. Circuit drawings (Fig. 9A-9W and Fig. 10A-10E, not shown) give details of the two chips. Instruction set.-Of the 13 bits I 0 -I 12 , I 12 is zero for a branch operation (conditional if I 11 is zero) in this case bits I 0 -I 10 forming the branch address (2 bits selecting a chip and 7 bits addressing the read-only memory). Otherwise bits I 0 -I 2 represent a S field, bits I 3 -I 6 an R field (both the R and S fields representing operation), bit I 7 a subtract field and bits I 8 -I 11 a mask field defining 13 possible digit masks. Timing.-The system operates on two external clocks (O1, 02, Fig. 5A, not shown) and two internally generated clocks (P 1 , P 2 ), each of which changes state in each state time. The state times count up from S 0 to S 15 whilst the D times (each representing an instruction cycle) counts down from D 15 to D 1 . Keyboard.-As well as the decimal numbers 0-9 and decimal point, 20 function keys are provided together with a decimal point position switch (which may be individual buttons or a thumb wheel). Keys are provided for rounding up/down, memory accumulation and designation of constants. It comprises a 15 x 7 matrix scanned by signals D 1 -D 15 and sensed as 7 outputs supplied on K lines (Fig. 2a) to the data chip. These signals are encoded into 3 bit binary code by encoder 400 (Fig. 2b4) into which it is entered at S 3 of every digit time. A 4 bit code representing D time is also formed and entered together with the 3 bit code into register 8 to form a readonly memory address. If for example the multiply key is operated an address for the read-only memory location containing the first instruction of the multiply routine is formed.