GB1442459A - Data processing system - Google Patents

Abstract

1442459 Data processing system INTERNATIONAL BUSINESS MACHINES CORP 3 Aug 1973 [15 Sept 1972] 37070/73 Heading G4A A data processing system includes control circuits arranged to operate, in response to system conditions and mode setting instructions arising during operation of the system, in a selected one of a plurality of modes in which instructions are interpreted differently. As described a processor 2 is connected to a processor 1 (shown in detail on the right) both processors being of similar construction. It is stated that the system may include further similar processors. Program instructions and data are read from store 11 into register 25 under the control of an address in register 22 which is read from store 68 and may subsequently be replaced in store 68 after modification in circuit 70 to form the address of the next required instruction or data word. Register 25 is connected by buses to execution unit 13 which includes register 33, 34, 38 and ALU 35, and to instruction decoders 71, 72, 73. The width of the horizontal bars at register 25 on the various buses indicates the portions of the contents of the register transferred to other parts of the processor. Mode circuits 80, 81, and 82 are used to select one of the instruction decoders which handle respective different instruction formats or interpret similar operation codes parts of instructions differently. The decoders supply control signals C to the remainder of the processor via OR unit 77. The mode circuits include two buffer registers 81, 82 (two being provided to enable successive instruction cycles to be overlapped) and a decoder 80 which energizes the appropriate one of decoders 71, 72, 73 in response to the contents of the buffers. The buffers may be loaded in response to instructions via bus 65, in response to various conditions arising within the processor via bus 87 as indicated by status bits in status registers 44, 90 or in response to external requests via unit 52 and bus 86, e.g. from I/O units. In this way the processor is switched to operate in a mode appropriate to the operations to be performed. When program branches occur which necessitate a mode change the previous mode control word from register 81 is loaded at a fixed location in store 11 for a subsequent return. It is stated that if the processor is as in Specification No. 1,313,951 where a set of registers is provided for each of several programs then loading of the mode control word into store is not necessary, each register set including a mode control register and the appropriate set being energized as required. When pure data words are read from store 11 into register 25 the control signals for the system are derived from implicit decoder 75 which is energized by the mode control circuits in response to mode signals derived from the preceding (instruction) word read into register 25. Processor 2 may take control of all or part of processor 1 by feeding the appropriate mode control signals to the MAST part of the mode circuits 80, 81, 82 via bus 108 to energize master decoder 75. The MAST part of the mode circuits override the INT parts so that processor 2 may take control at any time. Decoder 75 decodes instructions which are loaded in register 101, via register 100 to allow for overlap, by processor 2. Data may also be transferred to processor 1 via register 100. Processor 2 may take control of processor 1 to test the latter or to cause processor 1 to execute a job which it is itself not capable of executing. The arrangements allows the amount of program storage to be reduced, e.g. a single program may be stored to calculate n!, one of two instruction decoders being selected in accordance with whether the calculation is binary or decimal.