GB1418478A - Facsimile signal transmission system - Google Patents

Abstract

1418478 Copying by scanning MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 29 Nov 1972 [29 Nov 1971] 55023/72 Heading H4F In a facsimile transmitter each line of a document (25, Fig. 5, not shown) is repeatedly scanned, and the resulting signals due to sucessive marks and spaces are sequentially sampled, coded, and transmitted, only one mark or space signal being sampled during one line scan, the following space or mark signal only being sampled when the last digit of the previous coded signal is being transmitted; at the receiver, Fig. 12, the coded signals are decoded and used to control a cathode-ray tube 72 which repeatedly scans a line on a recording medium 73, but is only energized when the signal due to a black mark has been docoded; n - 1 mark and space signals are transmitted but the receiver operates to recover the nth mark or space signal by subtracting the length of the n - 1 signals from the length of a line, so that the last space or mark in each line need not be transmitted. In the described embodiment a mark or space signal of run length k (#3) is coded by taking the binary number of k - 1; this binary number has m digits and m - 1 zeros are added in front of the binary number k- 1, e.g. if k = 3, k - 1 = 2, binary k - 1= 10 so m=2, m-1=1, and the coded number =010. In the sampler and coder Fig. 6, a flip-flop 42 is set either by the output of a vertical sync signal generator 36 which produces a pulse to move the document in the frame scanning direction when a complete line has been coded or by the code completion output of a coding matrix 55. When flip-flop 42 is set, for one line scanning period, it enables an AND gate 31 to pass clock pulses to a counter 30. The count in counter 34 corresponds to the mark and space signals in that scanned line which have already been coded, and when the counts in counters 30 and 34 are equal a coincidence circuit 33 produces an output to set a flip-flop 38 which enables an AND gate 35 to pass clock pulses to counter 34 and, via a one-bit eliminator 50, to a shift register 51, flip-flop 38 being reset arid AND gate 35 disabled when a controller 39 detects the following space or mark signal. The clock pulses added by the shaft register 51 are coded by circuits 52, 53, 55 and the coded signals are fed to a modulator 15 for transmission. In the receiver. Fig. 12, the received signal is demodulated at 60 and the zeros of each received code are counted at 66, the number of zeros being supplied to a matrix 67 to write the remainder of the code into a shift register 68. Matrix 67 also provides an input to a controller 69 (also Fig. 15, not shown) which produces a gate pulse to enable an AND gate G1 to supply clock pulses to a counter 80. The count in a counter 81 corresponds to the mark and space signals in that scanned line which have already been decoded, and when the counts in counters 80 and 81 are equal a coincident circuit 82 produces an output to set flip-flop 83; when flip-flop 83 is set AND gate G2 is enabled to pass clock pulses to counter 81 and, via a one-bit eliminator 85 (as the number in shift register 68 is k - 1) to a counter 84. When the count in counter 84 equals the number in shift register 68 coincident circuit 86 provides an output to reset flip-flop 83. Flip-flop 83 thus produces an output whose length is equal to the run-length of the respective mark or space signal. The output of flip-flop 83 is fed to an AND gate G4, the other input of which, from a flip-flop 87, is "1" only if a mark signal is received, in which case a signal is supplied to the cathode-ray tube 72 to provide a mark on recording medium 73. To recover the nth mark or space signal the controller 69 includes a multivibrator (114, Fig. 15, not shown) and an AND gate (115) which, on receipt of a vertical synchronizing pulse from generator 64, prevent clearing of the counter 81 and resetting of the flip-flop 83.