GB1388966A - Television channel indicator - Google Patents

Abstract

1388966 Television channel indicator; cathode ray tube displays SHARP KK 2 March 1973 [3 March 1972] 10331/73 Heading H3Q and H4T A television channel indicator has a character generator 20 responsive to selection of a television channel to generate a character display on a television screen indicative of the channel selected. A switch 47, Fig. 6, is selected with moving the channel selector 3, Fig. 1, so as to programme a encoder 48 such as a diode matrix (Fig. 7, not shown), of a character selection circuit 19 to provide a coded signal output, from a decoder 49 such as a diode matrix, corresponding to the selected channel. The output from the character selection circuit 19 is supplied to a character generator 20 which feeds its output to a signal composition/substitution circuit 17 which enables the channel character indication, VHF channel number or UHF channel U and channel number (Fig. 5, not shown), to be displayed on the tube 7 with or without the video signal from a video amplifier 6 for a time determined by an indicator period setting circuit 18. The character generator 20 includes counters 50 and 53 operated by the vertical and horizontal pulses and from a pulse oscillator 52 having a high frequency compared to the horizontal scanning frequency, vertical and horizontal unit signal generators 51 and 54 formed by gates, segment character and character output signal generators 55, 56 and 57 formed of gates and an AND gate 58. The indicator period setting circuit 18 may be a one shot transistor multivibrator (Fig. 2, not shown) or a transistor Schmitt circuit (Fig. 3, not shown), with the delay period provided by discharge of a capacitor (43). In a modification to Fig. 6 (Fig. 10, not shown), when no synchronizing signals are detected the selection of the channel character signal is inhibited from the character generator 20 so as to prevent indication of that channel on the tube. The channel characters may be made to slant (Fig. 12, not shown), by including integration circuits 64, 65 and a comparison circuit 66 which may be transistor circuit (Fig. 14, not shown), used to control the pulse oscillator 52. With five horizontal scanning lines occurring during one vertical scanning period the integration circuit 64 provides five sawtooth outputs (Fig. 13, not shown), to one sawtooth output from the integration circuit 65. The comparator transistor 66 compares these sawtooth outputs and conducts for each of the horizontal pulses to provide five successively shorter duration output pulses during one vertical scanning period. The pulse oscillator 52, which includes NAND gates 84, 85 is energized by the output pulses from the comparator so as to enable formation of the slanting channel characters..