GB1384818A - Electrical capacitive storage cells - Google Patents

Abstract

1384818 Semi-conductor devices PLESSEY CO Ltd 8 Aug 1973 [18 Sept 1972] 43222/72 Heading H1K A plurality of capacitative storage cells are formed in a substrate 1 of a given conductivity type by diffused regions 2 of the opposite conductivity type and overlying capacitative electrodes 5. A magnetic field or an electric field if applied to the substrate to provide a bias such that minority carriers injected from one diffusion move to a particular neighbouring diffusion. The arrangement shown is a shift register (which in practice would have more storage cells) in which the bias is provided by a voltage source connected across contacts 7, 8. Information fed to one of the terminals 6 is shifted by clock pulses applied alternately to electrodes 5 such that when the potential applied to an electrode 5 is high and stored information is non-zero the corresponding PN junction 3 becomes forward biased and injects carriers in a number equivalent to the stored information into the substrate and these move in the bias field to be collected by the next diffusion, the electrode 5 of which is at that time at low potential. Losses in the substrate are reduced by the carrierreflecting NN<+> junction. The stored information, which may be in digital or analogue form, appears at the other terminal 6 and may be presented in electrical or optical form. Radiation could instead be used to supply the input information. Systems employing 3 clock pulse sources could replace the two pulse systems described, and a rectangular matrix of cells could use two electric fields, or one electric and one magnetic, to provide the perpendicular biases for the rows and columns. Fig. 5 shows a schematic arrangement for logic circuitry with three "first" cells A and a single "final" cell C. Stored charge from the A cells may be moved simultaneously or sequentially to the C cell. The logic operation performed depends on the relative capacitances of the cells. If all four cells are equivalent, the device is a 3 input OR gate; if cell C has twice the capacitance of each A cell the device is a 2-out-of-3-gate; and if cell C has three times the capacitance of each A cell, the device is an AND gate.