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GB1360094A - Data processing system - Google Patents

Data processing system

Info

Publication number
GB1360094A
GB1360094A GB4458171A GB4458171A GB1360094A GB 1360094 A GB1360094 A GB 1360094A GB 4458171 A GB4458171 A GB 4458171A GB 4458171 A GB4458171 A GB 4458171A GB 1360094 A GB1360094 A GB 1360094A
Authority
GB
United Kingdom
Prior art keywords
error
main processor
processor
data
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4458171A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19702048473 external-priority patent/DE2048473C3/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1360094A publication Critical patent/GB1360094A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1405Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

1360094 Error detection/correction INTERNATIONAL BUSINESS MACHINES CORP 24 Sept 1971 [2 Oct 1970] 44581/71 Heading G4A A data processing system includes a main processor HVS having a plurality of check circuits, and an error processor FVS operable to monitor the main processor check circuits and, in the event that it detects a signal indicating an error within the main processor, to obtain the source data involved from the main processor, compute the correct result from that data, transfer the correct result to the main processor and cause the latter to execute its next program step. The error processor may be a relatively simple serial machine connected to a disc file 3 from where it obtains an error routine and other data and to which it supplies data relating to the number and types of errors detected in the main processor (error logging). The error check circuits in the main processor may be parity circuits each having a unique address, the error processor being arranged to scan all the error check circuits in sequence in each cycle by applying their address in sequence to a decoder which enables a number of AND gates in sequence, the AND gates being connected via an OR gate to a bus which is connected to the error processor. A typical operating sequence is as follows. The main processor executes a microprogram step after which an error check is made. In the event of an error the error processor determines where the error occurred, initiates an error LOG routine, and accepts data from the main processor which will enable it to perform the erroneous step if necessary. The main processor is then instructed to repeat the step leading to the error. If this retry results in the same error the error processor performs the step and inserts the result into the appropriate unit in the main processor which is then instructed to perform the next microprogram step. When the error processor performs a step in this way it actuates the logging of the error on its associated disc file.
GB4458171A 1970-10-02 1971-09-24 Data processing system Expired GB1360094A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702048473 DE2048473C3 (en) 1970-10-02 Fault data computer of lower performance connected to a main data computer

Publications (1)

Publication Number Publication Date
GB1360094A true GB1360094A (en) 1974-07-17

Family

ID=5784022

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4458171A Expired GB1360094A (en) 1970-10-02 1971-09-24 Data processing system

Country Status (3)

Country Link
JP (1) JPS5133701B1 (en)
FR (1) FR2105868A5 (en)
GB (1) GB1360094A (en)

Also Published As

Publication number Publication date
FR2105868A5 (en) 1972-04-28
JPS5133701B1 (en) 1976-09-21
DE2048473B2 (en) 1975-04-03
DE2048473A1 (en) 1972-04-06

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee