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GB1351590A - Digital data storage addressing system - Google Patents

Digital data storage addressing system

Info

Publication number
GB1351590A
GB1351590A GB1247073A GB1247073A GB1351590A GB 1351590 A GB1351590 A GB 1351590A GB 1247073 A GB1247073 A GB 1247073A GB 1247073 A GB1247073 A GB 1247073A GB 1351590 A GB1351590 A GB 1351590A
Authority
GB
United Kingdom
Prior art keywords
gates
address
prefix
zero
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1247073A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1351590A publication Critical patent/GB1351590A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Storage Device Security (AREA)

Abstract

1351590 Data processing INTERNATIONAL BUSINESS MACHINES CORP 15 March 1973 [31 March 1972] 12470/73 Heading G4C In a digital data processing system in which a plurality of central processor units CPU1- CPUN (Fig. 1) have areas of main storage 200 assigned to them, (1) to access its assigned storage a CPU inserts a zero address in the higher order bits of its address register, this being modified by a prefix representing the base address of the assigned storage, the prefix being held in its control register, (2) to access the storage of CPU1, the prefix is entered into the address register, this being modified so that the higher order address bits applied to the main store are zero and (3) to access the storage when any other central processing unit the address bits in the address register are not changed. As described the modification of the address is effected by the logic circuitry of Fig. 3 in which when the higher order address bits on lines A8- A19 are all zero (i.e. when the processor is addressing its own storage) AND gates 12A- 12D are enabled by a negative signal on lead 11 and AND gates 8A-8D are enabled by a positive signal on lead 7 so that the prefix address bits P8-P19 are applied to the main store (since gates 8A-8D contribute only zeerso). When the bits on lines A8-A19 correspond to the prefix, gates 12 are disabled by a positive signal on lead 11 (since at least one of OR gates 10A-10B is enabled) and gates 8A-8D are disabled by a negative signal on lead 7 (since the outputs of exclusive OR gates 4A-4D are "zero") so that output lines 16A-16D are forced to their zero state. When a value other than zero or the prefix is applied to lines A8- A19 at least one OR gate 10A-10B is enabled to disable the AND gates 12A-12D and at least one of the exclusive OR gates 4A-4D is enabled to enable associated OR gates 6A-6B to provide an enabling input to AND gates 8A-8D so that the address bits on lines A8- A19 are applied unchanged.
GB1247073A 1972-03-31 1973-03-15 Digital data storage addressing system Expired GB1351590A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US23989472A 1972-03-31 1972-03-31

Publications (1)

Publication Number Publication Date
GB1351590A true GB1351590A (en) 1974-05-01

Family

ID=22904179

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1247073A Expired GB1351590A (en) 1972-03-31 1973-03-15 Digital data storage addressing system

Country Status (6)

Country Link
JP (1) JPS5231138B2 (en)
CA (1) CA985425A (en)
DE (1) DE2311503C2 (en)
FR (1) FR2179384A5 (en)
GB (1) GB1351590A (en)
IT (1) IT976393B (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH613540A5 (en) * 1975-02-26 1979-09-28 Siemens Ag
US4212057A (en) * 1976-04-22 1980-07-08 General Electric Company Shared memory multi-microprocessor computer system
JPS5354783A (en) * 1976-10-28 1978-05-18 Terasaki Denki Sangyo Kk Vacuum switch
JPS54104253A (en) * 1978-02-03 1979-08-16 Hitachi Ltd Information processor
US4209839A (en) * 1978-06-16 1980-06-24 International Business Machines Corporation Shared synchronous memory multiprocessing arrangement
JPS55105763A (en) * 1979-02-05 1980-08-13 Fanuc Ltd Address instruction system
JPS55116296U (en) * 1979-02-09 1980-08-16
JPS55134458A (en) * 1979-04-04 1980-10-20 Hitachi Ltd Memory access system of multiprocessor system
JPS564854A (en) * 1979-06-22 1981-01-19 Fanuc Ltd Control system for plural microprocessors
JPS5875121U (en) * 1981-11-16 1983-05-20 石川島芝浦機械株式会社 Tractor hydraulic operating device
JPS608971A (en) * 1983-06-29 1985-01-17 Toshiba Corp Central processing unit
JPS6010382A (en) * 1983-06-30 1985-01-19 Toshiba Corp Central processing unit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3505647A (en) * 1966-04-18 1970-04-07 Gen Electric Apparatus providing alterable symbolic memory addressing in a multiprogrammed data processing system
US3555513A (en) * 1967-10-11 1971-01-12 Burroughs Corp Multiprocessor digital computer system with address modification during program execution

Also Published As

Publication number Publication date
CA985425A (en) 1976-03-09
DE2311503A1 (en) 1973-10-04
DE2311503C2 (en) 1983-11-10
FR2179384A5 (en) 1973-11-16
JPS5231138B2 (en) 1977-08-12
JPS499938A (en) 1974-01-29
IT976393B (en) 1974-08-20

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee