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GB1309090A - Logic gating circuits - Google Patents

Logic gating circuits

Info

Publication number
GB1309090A
GB1309090A GB1309090DA GB1309090A GB 1309090 A GB1309090 A GB 1309090A GB 1309090D A GB1309090D A GB 1309090DA GB 1309090 A GB1309090 A GB 1309090A
Authority
GB
United Kingdom
Prior art keywords
transistor
input
circuit
charge
gating circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Co Ltd filed Critical Marconi Co Ltd
Publication of GB1309090A publication Critical patent/GB1309090A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/084—Diode-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

1309090 Transistor logic circuits MARCONI CO Ltd 3 Nov 1970 [2 Dec 1969] 58693/69 Heading H3T A logic circuit such as a NAND gate has a capactior C11 charged by a device such as a transistor T11, its charge controlling via a unidirectionally conducting device such as D112 the conduction of a transistor T12 in series with a further transistor T13, and the input signals being received at the junction of T11-C11. Thus only if all inputs are high are input diodes D11 D12 non-conductive, so that the charge which is accumulated on C11 during the period of a # 1 pulse applied to T11 base is not discharged. Consequently T12 is biased to conduct by a diode D112, to provide a current path between T13 which conducts in # 4 time, and the input at D21 of a further similar circuit. The further circuit is gated by # 2 # 3 and acts as an inverter to give a delayed AND output.
GB1309090D 1969-12-02 1969-12-02 Logic gating circuits Expired GB1309090A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5869369 1969-12-02

Publications (1)

Publication Number Publication Date
GB1309090A true GB1309090A (en) 1973-03-07

Family

ID=10482200

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1309090D Expired GB1309090A (en) 1969-12-02 1969-12-02 Logic gating circuits

Country Status (1)

Country Link
GB (1) GB1309090A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1441442A1 (en) * 2003-01-21 2004-07-28 Hewlett-Packard Development Company, L.P. A low power logic gate
WO2006096832A2 (en) * 2005-03-08 2006-09-14 Pnp Networks, Inc., A California Corporation Eas tag polling system
DE102005053747A1 (en) * 2005-11-10 2007-05-16 Georg Bedenk Logic circuit for use in microprocessor, has four switching units, out of which two of switching units have control input for delivering clock signal, which determines whether two switching units are opened/closed
DE102005053740A1 (en) * 2005-11-10 2007-05-16 Georg Bedenk Logic circuit for use in microprocessor for execution of NAND operation, has logic units provided with inputs for supplying clock pulse in order to determine whether logic units are opened or closed

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1441442A1 (en) * 2003-01-21 2004-07-28 Hewlett-Packard Development Company, L.P. A low power logic gate
WO2006096832A2 (en) * 2005-03-08 2006-09-14 Pnp Networks, Inc., A California Corporation Eas tag polling system
WO2006096832A3 (en) * 2005-03-08 2009-04-16 Pnp Networks Inc A California Eas tag polling system
US7755485B2 (en) * 2005-03-08 2010-07-13 Inpoint Systems, Inc. System and method for electronic article surveillance
DE102005053747A1 (en) * 2005-11-10 2007-05-16 Georg Bedenk Logic circuit for use in microprocessor, has four switching units, out of which two of switching units have control input for delivering clock signal, which determines whether two switching units are opened/closed
DE102005053740A1 (en) * 2005-11-10 2007-05-16 Georg Bedenk Logic circuit for use in microprocessor for execution of NAND operation, has logic units provided with inputs for supplying clock pulse in order to determine whether logic units are opened or closed

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees