GB1285355A - Memory addressing device for use in a data-processing system - Google Patents

Abstract

1285355 Memory accessing PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 28 Oct 1969 [31 Oct 1968] 52763/69 Headings G4A and G4C The memory of a data processing system is divided into tables which may contain operands or reference addresses for further tables and is accessed in response to the additive combination of a portion of an instruction, which may itself have been accessed from the memory, the portion defining the location of a word within a table, and a word accessed from the memory which defines the address (reference address) in the memory of the base of the table within which the required word is located, the portion of the instruction being determined by a masking register. An embodiment of a data-processing system utilizing such a procedure is shown in Fig. 5. In operation an instruction register itis incremented causing an instruction to be accessed from the memory M and loaded in the register MR which contains a flag field indicating whether the addressing can be completed using this instruction or whether a further instruction will be required. The instruction is then passed to register CR with the exception of an operation code field which is passed to decoder OPCDEC. Register MR is then filled from the auxiliary register HR with the address in the memory of the base of the first table to be used. The mask register MK is then loaded with a field of "1"s equal in length to the length of the address components in the instruction which specify the locations of required address within the table specified by the contents of register MR. The contents of MR are then added in adder AD to the masked portion of the contents of register CR to form the address of a word within the memory. The word is then read out into register MR (using the memory address register SEL) the mask bits are shifted to select the next portion of the contents of register CR and the procedure is repeated so long as an uninterrupted sequence of non-zero portions of the contents of register CR is available. When a zero portion is detected, or all the portions of the register CR are exhausted then, depending on the contents of the flag field now contained in register CR, the process terminates the desired word having been found (i.e. the table which has been located in a operand table as opposed to a reference table) or the instruction register IT is incremented, a new instruction accessed, and the process repeated. In a further embodiment each address component in register CR has a different field length specified by a flag field CRL. This flag field is gated to a control circuit SPS to appropriately control the length of the mask field at each step. The process may be indirect with the field CRL accessing the appropriate masking fields from the memory and gating them to the masking register MK. In a further embodiment the lengths of the address components in register CR are checked against an appropriate table in the memory. A further adder is provided together with a sign detector for determining whether the difference in the lengths is positive or negative, an overflow table being accessed (in a manner similar to that described above) and utilized in the case where the address components are too long. The type of table, e.g. read only, not to be used for a - particular program, operand table, reference table &c., is also specified by a field. The specification describes the arrangement in some details and gives microprograms for the addressing operations. The microprograms include steps for use when the memory employs destructive readout, the contents of the registers after having been accessed from the memory being written back where appropriate.