GB1260777A - Improvements in or relating to memory cells - Google Patents
Improvements in or relating to memory cellsInfo
- Publication number
- GB1260777A GB1260777A GB37782/70A GB3778270A GB1260777A GB 1260777 A GB1260777 A GB 1260777A GB 37782/70 A GB37782/70 A GB 37782/70A GB 3778270 A GB3778270 A GB 3778270A GB 1260777 A GB1260777 A GB 1260777A
- Authority
- GB
- United Kingdom
- Prior art keywords
- fet
- parent specification
- memory cells
- line
- relating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
- H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
Landscapes
- Static Random-Access Memory (AREA)
Abstract
1,260,777. Memory cells. MARCONI CO. Ltd. 5 Aug., 1970, No. 37782/70. Addition to 1,260,426. Heading H3T. [Also in Division G4] In a memory cell as in the parent Specification in which the first and second signal access lines 12, 13 are connectable through FET's 15, 16 to the third line 14, a further selectably low impedance device such as FET 18 is arranged between the FET's 15, 16 and the line 14. Also the "pull down" FET's 8, 9 and 10, 11 are across the loads 4, 5 not the cross-coupled FET's 1, 2. When writing, the FET 18 is kept non-conductive by a Ov gate bias, and the lines 12, 14 or 13, 14 taken negative to set one state or the other. When reading or searching, FET 18 is made conductive by -20V on the gate, and operation continues as described in the parent Specification. Operating voltages are in some cases different from those in the parent Specification.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB37782/70A GB1260777A (en) | 1969-08-18 | 1970-08-05 | Improvements in or relating to memory cells |
US89204A US3693170A (en) | 1970-08-05 | 1970-11-13 | Memory cells |
IT67336/71A IT991502B (en) | 1970-08-05 | 1971-02-01 | MEMORY DEVICE |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB41076/69A GB1260426A (en) | 1969-08-18 | 1969-08-18 | Improvements in or relating to memory cells |
GB37782/70A GB1260777A (en) | 1969-08-18 | 1970-08-05 | Improvements in or relating to memory cells |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1260777A true GB1260777A (en) | 1972-01-19 |
Family
ID=42245946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB37782/70A Expired GB1260777A (en) | 1969-08-18 | 1970-08-05 | Improvements in or relating to memory cells |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1260777A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4442508A (en) * | 1981-08-05 | 1984-04-10 | General Instrument Corporation | Storage cells for use in two conductor data column storage logic arrays |
-
1970
- 1970-08-05 GB GB37782/70A patent/GB1260777A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4442508A (en) * | 1981-08-05 | 1984-04-10 | General Instrument Corporation | Storage cells for use in two conductor data column storage logic arrays |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |