GB1256221A - Improvements relating to binary multiplication circuits - Google Patents

Abstract

1,256,221. Multiplying apparatus. BRITISH AIRCRAFT CORP. Ltd. 6 March, 1969 [7 Dec., 1967], No. 55685/67. Heading G4A. In a binary multiplier suitable for multiplying a multiplicand A set into a shift-register a n ... a 0 , Fig. 1, by a fixed multiplier predetermined by organizational logic, the multiplicand is successively shifted to the right in the direction of decreasing significance and each bit, as it reaches the lowest-order stage a 0 is used to control the addition of the fixed multiplier into an accumulating register c 0 , ... c k , b 0 , the contents of which are right-shifted prior to each addition, with the least significant bit being shifted into an output shift-register. When the multiplicand A has been completely shifted through its shift register (n shifts), the product appears in the double length register comprising the accumulating register and the output register. The sequence of operations for a multiplicand of, for example 5 (=101) and a fixed multiplier of 15 (=1111) is shown in the following table In this table the successive contents of the registers are shown in rows (1), (2), (3) and (4), the intervening rows being inserted to show the principle employed, although the register c 0 ... c 3 , b 0 , never actually registers these values. Logic tables, and outline logic circuitry, are given, for determining the successive contents of the register c 0 ... c 3 , b 0 .