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GB1211412A - Improvements in and relating to semiconductor devices - Google Patents

Improvements in and relating to semiconductor devices

Info

Publication number
GB1211412A
GB1211412A GB3678/68A GB367868A GB1211412A GB 1211412 A GB1211412 A GB 1211412A GB 3678/68 A GB3678/68 A GB 3678/68A GB 367868 A GB367868 A GB 367868A GB 1211412 A GB1211412 A GB 1211412A
Authority
GB
United Kingdom
Prior art keywords
transistors
projections
copper
conductive tracks
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3678/68A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1211412A publication Critical patent/GB1211412A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

1,211,412. Semi-conductor devices; circuit assemblies. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 24 Jan., 1968 [27 Jan., 1967], No. 3678/68. Headings H1K and H1R. A support for one or more transistors or monolithic integrated circuits comprises an insulating substrate with projections constituted by conductive layers electroplated to a thickness exceeding that of the transistors or circuits which are to be mounted between the projections with their supply conductors electrically connected to them. The supports can be made in multiple from a borosilicate glass or enamelled ceramic plate by first vapour depositing through a metal mask to form a repeating pattern of conductive tracks 35, 36, 37 (Fig. 6) consisting of 1-2Á thick aluminiumchromium with a 200 A‹ overlayer of chromium. Then the entire surface is coated by vapour deposition with copper which is thickened by electroplating either before or after provision of a photo-resist mask exposing only the sites of the projections. The copper on the unmasked areas is then electroplated with a 2-3Á layer of gold. After removing the photo-resist the plate is etched in nitric acid to remove the copper save where it is protected by the gold. After ultrasonically soldering the terminals of transistors 34 to the conductive tracks and coating with resin the plate is sawn up into single units. In another method the conductive tracks are made by depositing goldcoated chromium overall and then patterning by etching with aqua regia through a photoresist mask. If desired, a plurality of transistors and associated circuit elements are attached to each unit of the support with the projections attached to the terminals of the elementary circuits thus formed. The supports are intended for soldering in an inverted position on hybrid circuit boards.
GB3678/68A 1967-01-27 1968-01-24 Improvements in and relating to semiconductor devices Expired GB1211412A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6701294A NL6701294A (en) 1967-01-27 1967-01-27

Publications (1)

Publication Number Publication Date
GB1211412A true GB1211412A (en) 1970-11-04

Family

ID=19799151

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3678/68A Expired GB1211412A (en) 1967-01-27 1968-01-24 Improvements in and relating to semiconductor devices

Country Status (7)

Country Link
AT (1) AT286416B (en)
BE (1) BE709891A (en)
CH (1) CH483774A (en)
DE (1) DE1285581C2 (en)
FR (1) FR1553301A (en)
GB (1) GB1211412A (en)
NL (1) NL6701294A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0355424B1 (en) * 1988-07-25 1995-02-15 Asahi Glass Company Ltd. Glass antenna device for an automobile
US4933812A (en) * 1989-10-11 1990-06-12 Hewlett-Packard Company Package and circuit arrangement for housing and connecting polarized electrical components and method of manufacture

Also Published As

Publication number Publication date
FR1553301A (en) 1969-01-10
AT286416B (en) 1970-12-10
NL6701294A (en) 1968-07-29
DE1285581C2 (en) 1973-08-23
CH483774A (en) 1969-12-31
DE1285581B (en) 1968-12-19
BE709891A (en) 1968-07-25

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees