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GB1208576A - Methods of manufacturing semiconductor devices - Google Patents

Methods of manufacturing semiconductor devices

Info

Publication number
GB1208576A
GB1208576A GB27239/70A GB2723970A GB1208576A GB 1208576 A GB1208576 A GB 1208576A GB 27239/70 A GB27239/70 A GB 27239/70A GB 2723970 A GB2723970 A GB 2723970A GB 1208576 A GB1208576 A GB 1208576A
Authority
GB
United Kingdom
Prior art keywords
layer
silicon
oxide
sunk
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB27239/70A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NL666614016A external-priority patent/NL153374B/en
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1208576A publication Critical patent/GB1208576A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

1,208,576. Semi-conductor devices. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 2 Oct., 1967 [5 Oct., 1966], No. 27239/70. Divided out of 1,208,574. Heading H1K. A method of manufacturing a semi-conductor device having a substantially flat silicon oxide surface layer comprises subjecting a silicon layer on a substrate to an oxidizing treatment whilst a selected portion of its surface is masked against oxidation by means of a masking layer, and causing an oxide of silicon to grow into the silicon layer at the unmasked portions until the grown oxide forms a layer which is sunk over at least part of its thickness in the silicon layer. During the oxidizing process the formation of the silicon oxide layer may be interrupted to etch away the oxide layer so far formed, at least for part of its thickness, so that the final layer can be sunk to a greater depth than otherwise. The method is used for the production of isolating walls between circuit elements formed in the silicon layer, the isolating walls being sunk throughout the silicon layer. Specifications 1,208,574, 1,208,575, 1,208,577 and 1,208,578 are referred to.
GB27239/70A 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices Expired GB1208576A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL666614016A NL153374B (en) 1966-10-05 1966-10-05 PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE PROVIDED WITH AN OXIDE LAYER AND SEMI-CONDUCTOR DEVICE MANUFACTURED ACCORDING TO THE PROCEDURE.
GB44763/67A GB1208574A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
GB1208576A true GB1208576A (en) 1970-10-14

Family

ID=26265451

Family Applications (4)

Application Number Title Priority Date Filing Date
GB27516/70A Expired GB1208577A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB27238/70A Expired GB1208575A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB27239/70A Expired GB1208576A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB27517/70A Expired GB1208578A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Family Applications Before (2)

Application Number Title Priority Date Filing Date
GB27516/70A Expired GB1208577A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices
GB27238/70A Expired GB1208575A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB27517/70A Expired GB1208578A (en) 1966-10-05 1967-10-02 Methods of manufacturing semiconductor devices

Country Status (1)

Country Link
GB (4) GB1208577A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2441170A1 (en) * 1973-09-07 1975-03-13 Philips Nv METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT
US6093620A (en) * 1971-02-02 2000-07-25 National Semiconductor Corporation Method of fabricating integrated circuits with oxidized isolation

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054450A (en) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US4592128A (en) * 1984-06-04 1986-06-03 Inmos Corporation Method for fabricating integrated circuits with polysilicon resistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093620A (en) * 1971-02-02 2000-07-25 National Semiconductor Corporation Method of fabricating integrated circuits with oxidized isolation
DE2441170A1 (en) * 1973-09-07 1975-03-13 Philips Nv METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT

Also Published As

Publication number Publication date
GB1208578A (en) 1970-10-14
GB1208577A (en) 1970-10-14
GB1208575A (en) 1970-10-14

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PE20 Patent expired after termination of 20 years
PE20 Patent expired after termination of 20 years
PE20 Patent expired after termination of 20 years

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