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GB1186625A - Improvements in and relating to Semiconductor Devices - Google Patents

Improvements in and relating to Semiconductor Devices

Info

Publication number
GB1186625A
GB1186625A GB43772/67A GB4377267A GB1186625A GB 1186625 A GB1186625 A GB 1186625A GB 43772/67 A GB43772/67 A GB 43772/67A GB 4377267 A GB4377267 A GB 4377267A GB 1186625 A GB1186625 A GB 1186625A
Authority
GB
United Kingdom
Prior art keywords
layer
oxide layer
openings
etched
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB43772/67A
Inventor
Boyd Gordon Watkins
Michael Joseph Selser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxar Space LLC
Original Assignee
Philco Ford Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philco Ford Corp filed Critical Philco Ford Corp
Publication of GB1186625A publication Critical patent/GB1186625A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/40Resistors
    • H10D1/47Resistors having no potential barriers
    • CCHEMISTRY; METALLURGY
    • C11ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11CFATTY ACIDS FROM FATS, OILS OR WAXES; CANDLES; FATS, OILS OR FATTY ACIDS BY CHEMICAL MODIFICATION OF FATS, OILS, OR FATTY ACIDS OBTAINED THEREFROM
    • C11C5/00Candles
    • C11C5/002Ingredients
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/62Electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Oil, Petroleum & Natural Gas (AREA)
  • Wood Science & Technology (AREA)
  • Organic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Fats And Perfumes (AREA)
  • Drying Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

1,186,625. Semi-conductor devices; resistors. PHILCO-FORD CORP. 26 Sept., 1967 [26 Sept., 1966; 17 Nov., 1966], No. 43772/67. Headings H1K and H1S. A semi-conductor device comprises a body of semi-conductor material, an oxide layer on a surface of the body, and a layer of polycrystalline silicon on a surface of the oxide layer, the silicon forming a resistor or the insulated gate of a field effect transistor. In a preferred method of making the device, a monocrystalline silicon wafer 30 (Fig. 8) is provided with a grown or deposited silicon dioxide layer 31, a polycrystalline silicon layer 35 and a further oxide layer 36, and openings 38, 39 are etched in the layer 36 to expose the layer 35 and surround a gate region G and a resistor region R. Openings 41, 42 are then etched in the layer 35 with a solution comprising 15 parts (by volume) of concentrated nitric acid, 5 parts of glacial acetic acid and 2 parts of concentrated hydrofluoric acid using the oxide layer 36 as a mask, and openings 44a, 44b (Fig. 10) are etched in the first oxide layer 31 to expose the portions of the silicon wafer 30 which are to form the source and drain regions of the transistor. At the same time the portion of the oxide layer 36 above the gate region is removed and openings 45 are etched in this layer where the resistor contact pads are to be formed. The device is next subjected to a boron diffusion, e.g. by heating it to 1150‹ C. for 60 minutes in an atmosphere containing boron trichloride, oxygen and a carrier gas so that source and drain regions 50,51 (Fig. 16) are provided in the wafer 30 and the gate. and the resistor contact. pads axe doped to a low resistivity. Another oxide layer 55 is then grown and partially removed to form openings (60-64, Fig. 15, not shown) and aluminium 70 is vapour deposited to contact the source and drain regions and the gate and resistor contact pads through the openings. Finally, the aluminium is selectively removed to form the required contact pattern. A plurality of devices may be formed simultaneously in a single wafer which is subsequently diced, and each die may be encapsulated in borosilicate glass and sealed in a header. Portions of the layer 35 may be used as crossunders where needed.
GB43772/67A 1966-09-26 1967-09-26 Improvements in and relating to Semiconductor Devices Expired GB1186625A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58205366A 1966-09-26 1966-09-26
US59516366A 1966-11-17 1966-11-17

Publications (1)

Publication Number Publication Date
GB1186625A true GB1186625A (en) 1970-04-02

Family

ID=27078481

Family Applications (1)

Application Number Title Priority Date Filing Date
GB43772/67A Expired GB1186625A (en) 1966-09-26 1967-09-26 Improvements in and relating to Semiconductor Devices

Country Status (2)

Country Link
DE (3) DE1789194B1 (en)
GB (1) GB1186625A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2020531A1 (en) * 1970-04-27 1971-11-18 Siemens Ag Method for manufacturing a semiconductor component
EP0090520A2 (en) * 1982-03-26 1983-10-05 Kabushiki Kaisha Toshiba A method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate
US5731240A (en) * 1991-07-24 1998-03-24 Canon Kabushiki Kaisha Manufacturing method for semiconductor depositing device
WO2009030336A1 (en) * 2007-08-31 2009-03-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Circuit arrangement and method for the encapsulation thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4982257A (en) * 1972-12-12 1974-08-08

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189973A (en) * 1961-11-27 1965-06-22 Bell Telephone Labor Inc Method of fabricating a semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2020531A1 (en) * 1970-04-27 1971-11-18 Siemens Ag Method for manufacturing a semiconductor component
EP0090520A2 (en) * 1982-03-26 1983-10-05 Kabushiki Kaisha Toshiba A method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate
EP0090520B1 (en) * 1982-03-26 1989-05-31 Kabushiki Kaisha Toshiba A method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate
US5731240A (en) * 1991-07-24 1998-03-24 Canon Kabushiki Kaisha Manufacturing method for semiconductor depositing device
WO2009030336A1 (en) * 2007-08-31 2009-03-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Circuit arrangement and method for the encapsulation thereof

Also Published As

Publication number Publication date
DE1589852B2 (en) 1979-08-02
DE1589852A1 (en) 1970-08-06
DE158928C (en)
DE1789194B1 (en) 1980-04-10

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLE Entries relating assignments, transmissions, licences in the register of patents
429A Application made for amendment of specification (sect. 29/1949)
429H Application (made) for amendment of specification now open to opposition (sect. 29/1949)
429D Case decided by the comptroller ** specification amended (sect. 29/1949)
SPA Amended specification published
PE20 Patent expired after termination of 20 years