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GB1173796A - A Circuit Arrangement for Determining an Optimum Path - Google Patents

A Circuit Arrangement for Determining an Optimum Path

Info

Publication number
GB1173796A
GB1173796A GB9036/67A GB903667A GB1173796A GB 1173796 A GB1173796 A GB 1173796A GB 9036/67 A GB9036/67 A GB 9036/67A GB 903667 A GB903667 A GB 903667A GB 1173796 A GB1173796 A GB 1173796A
Authority
GB
United Kingdom
Prior art keywords
node
elements
loop
stable
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB9036/67A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Safran Aircraft Engines SAS
Original Assignee
Societe Nationale dEtude et de Construction de Moteurs dAviation SNECMA
SNECMA SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Societe Nationale dEtude et de Construction de Moteurs dAviation SNECMA, SNECMA SAS filed Critical Societe Nationale dEtude et de Construction de Moteurs dAviation SNECMA
Publication of GB1173796A publication Critical patent/GB1173796A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06QINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management
    • G06Q10/06Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
    • GPHYSICS
    • G08SIGNALLING
    • G08GTRAFFIC CONTROL SYSTEMS
    • G08G1/00Traffic control systems for road vehicles
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/0016Arrangements providing connection between exchanges

Landscapes

  • Engineering & Computer Science (AREA)
  • Business, Economics & Management (AREA)
  • Entrepreneurship & Innovation (AREA)
  • General Physics & Mathematics (AREA)
  • Strategic Management (AREA)
  • Physics & Mathematics (AREA)
  • Economics (AREA)
  • Human Resources & Organizations (AREA)
  • Development Economics (AREA)
  • Tourism & Hospitality (AREA)
  • Educational Administration (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Marketing (AREA)
  • Operations Research (AREA)
  • Quality & Reliability (AREA)
  • Game Theory and Decision Science (AREA)
  • General Business, Economics & Management (AREA)
  • Theoretical Computer Science (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Traffic Control Systems (AREA)
  • Air Bags (AREA)
  • Feedback Control In General (AREA)
  • Train Traffic Observation, Control, And Security (AREA)

Abstract

1,173,796. Determining optimum path; road traffic signalling. SOC. NATIONALE D'- ETUDE ET DE CONSTRUCTION DE MOTEURS D'AVIATION. 24 Feb., 1967 [26 Feb., 1966], No. 9036/67. Headings G4A, G4P and G4Q. Problems of the optimum path type are solved using a circuit network with means for determining the shortest signal path therethrough. The network comprises node elements linked by so-called loop elements. One or more node elements are selected as arrival nodes and one or more as departure nodes, the problem being to determine the shortest path between a departure node and an arrival node, each loop element being weightable to impose a predetermined delay on signals. A clock generator applies clock pulses to all the node elements simultaneously, then all the loop elements simultaneously, then all the node elements &c. A node element can be enabled in which case the next application of a clock pulse thereto will set a bi-stable therein. A loop element can also be enabled in which case, if the element is weighted, subsequent clock pulses applied thereto will be counted (binary counter) and when a predetermined count is reached the next clock pulse applied will set a bi-stable in the loop element. If the loop element is unweighted (no counter) the first clock pulse applied after enablement will set the bi-stable. Initially all the arrival node elements, are enabled simultaneously. When the bi-stable in a node element is set it enables all loop elements (in any) fed from the node element (the loop elements are oriented in this sense, though loop elements oriented in opposite directions may be connected between any two node elements) and disables any loop elements feeding this node element. When the bistable in a loop element is set it enables, via an OR gate if necessary, the node element fed from the loop element. In this way signals progress through the network from the arrival nodes. The first departure node to have its bi-stable set terminates the above process and causes a signal to be transmitted back via the sequence of node and loop elements concerned to the particular arrival node whose initial enablement ultimately caused the setting of the bi-stable in the departure node. This transmission back, which causes the path to be displayed, can go through a given loop element only if its bi-stable is set (as it will be along the desired path) and an inhibition signal is absent. This inhibition signal can be applied to eliminate some paths (from a loop element bi-stable in the retained path) if more than one path would otherwise be displayed, i.e. a plurality of paths are equally optimum. Transmission through the node elements is immediate and unconditional, or may be blocked and delayed in bi-stables. Provision is also made for preventing the original enablement of any loop elements, to effectively remove them from the network. The network can be implemented using electronic, electromechanical, mechanical, hydraulic or pneumatic means. One application is traffic control, the node elements representing points where traffic jams are likely to occur, and the loop elements representing routes between them. The optimum path (route) determined is used to control luminous or electromechanical signals at cross-roads.
GB9036/67A 1966-02-26 1967-02-24 A Circuit Arrangement for Determining an Optimum Path Expired GB1173796A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR51268A FR1483778A (en) 1966-02-26 1966-02-26 Optimal path search method and device

Publications (1)

Publication Number Publication Date
GB1173796A true GB1173796A (en) 1969-12-10

Family

ID=8602380

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9036/67A Expired GB1173796A (en) 1966-02-26 1967-02-24 A Circuit Arrangement for Determining an Optimum Path

Country Status (4)

Country Link
US (1) US3558868A (en)
DE (1) DE1549525B1 (en)
FR (1) FR1483778A (en)
GB (1) GB1173796A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2085153B1 (en) * 1969-10-14 1974-07-12 Sncf
FR2093080A5 (en) * 1970-06-01 1972-01-28 Snecma
DE2106257A1 (en) * 1971-02-10 1972-08-24 Philips Patentverwaltung Computer educational game
JPS5437276B2 (en) * 1971-12-30 1979-11-14
US3939336A (en) * 1974-01-11 1976-02-17 Vsevolod Viktorovich Vasiliev Apparatus for analysis of network diagrams
US4830486A (en) * 1984-03-16 1989-05-16 Goodwin Frank E Frequency modulated lasar radar
FR2618007B1 (en) * 1987-07-06 1989-12-08 Vassor Bertrand METHOD AND DEVICE FOR SEARCHING THE OPTIMAL PATH BETWEEN TWO POINTS OF A MESH NETWORK
FR2621414B1 (en) * 1987-10-05 1990-01-12 Simon Philippe LUMINOUS PLAN WITH ELECTRONIC CONTROL SELECTOR
US5548773A (en) * 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3053453A (en) * 1957-10-15 1962-09-11 Armour Res Found Means for network computation
US3250902A (en) * 1962-05-16 1966-05-10 Mauchly Associates Inc Non-linear network computer
US3289323A (en) * 1962-11-21 1966-12-06 John W Fondahl Project network analyzing method and apparatus
CH451575A (en) * 1964-09-02 1968-05-15 Rueegg Naegeli & Cie Ag Planning device for workflow network plans
FR1452007A (en) * 1965-02-12 1966-02-25 Method and apparatus for calculations related to graphs

Also Published As

Publication number Publication date
DE1549525B1 (en) 1970-06-04
FR1483778A (en) 1967-06-09
US3558868A (en) 1971-01-26

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees