GB1159854A - Analogue-to-Digital Converter for Wide Band Signals - Google Patents

Abstract

1,159,854. A/D converters. INTERNATIONAL STANDARD ELECTRIC CORP. 28 July, 1967 [30 Aug., 1966], No. 34813/67. Heading G4H. An analog to digital converter, of the type in which samples of an analog signal ec (Fig. 2) are sequentially fed to comparator circuits M1-Mm under the control of a sampling selector C3 and compared with a reference sawtooth waveform Z, coincidence signals being generated when the amplitudes of the analog samples are equal to the sawtooth signal, includes a binary coding counter C2, the state of which represents the instantaneous amplitude of the reference signal, the count in the counter being read into a line in a memory MR when a coincidence signal from the associated comparator occurs. In the embodiment described the coding counter controls by a decoder D the rise and fall times of the sawtooth signal Z. Each of the comparator circuits M1-Mm is enabled during one of m time intervals S1-Sm so that a capacitor in each circuit, e.g. capacitor SH (Fig. 4) in circuit Mj is charged to the value of the associated input sample. Although coincidence may occur between the sawtooth signal and the input signal whilst the capacitor is charging up, no enabling signal is then fed to the memory since it is blocked at AND gate P3 by the signal Sj. If the jth sample of the input signal ec is greater than the value of the sawtooth signal at the end of time intervals Sj, a coincidence signal occurs during one of the subsequent time intervals S and the count in counter C2 is then transferred into line j of memory MR and read out to a register RS during the time interval Sj of the next cycle of the sawtooth waveform. If the sample is less than the value of the sawtooth signal at the end of a time interval Sj no count is transferred to the memory until one of the time intervals Sm ... Sj -1 of the next cycle of sawtooth waveform Z (only Sm -1 samples being read in for each cycle). A coincidence signal from the jth comparator then occurs, the count in counter C2 being transferred to the line j of memory MR and read out during the time interval Sj of that cycle.