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GB1148245A - Method and apparatus for timing pulse synchronisation - Google Patents

Method and apparatus for timing pulse synchronisation

Info

Publication number
GB1148245A
GB1148245A GB1554867A GB1554867A GB1148245A GB 1148245 A GB1148245 A GB 1148245A GB 1554867 A GB1554867 A GB 1554867A GB 1554867 A GB1554867 A GB 1554867A GB 1148245 A GB1148245 A GB 1148245A
Authority
GB
United Kingdom
Prior art keywords
pulse
unit
monostable
bistable
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1554867A
Inventor
Thua-Liet Dao
Boris Sakic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BBC Brown Boveri AG Switzerland
Original Assignee
BBC Brown Boveri AG Switzerland
Brown Boveri und Cie AG Switzerland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BBC Brown Boveri AG Switzerland, Brown Boveri und Cie AG Switzerland filed Critical BBC Brown Boveri AG Switzerland
Publication of GB1148245A publication Critical patent/GB1148245A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

1,148,245. Automatic phase control systems. BROWN, BOVERI & CO. Ltd. 5 April, 1967 [7 April, 1966], No. 15548/67. Heading H3A. The output of a divider 3 fed from a clock pulse generator 1 is synchronized with incoming binary data on line 12 by adding or deleting a pulse from the divider in accordance with the sense of the phase error. Outputs (B, C, D, Fig. 2, not shown) from the last three stages of the counter are combined in logic circuit 8 to develop pulses (a and b, Fig. 2) which overlap at the instant when an input pulse should arrive. These pulses on lines 9 and 10 condition a bi-stable 11 for operation by a pulse from unit 13; a monostable 18 is conditioned by a pulse from unit 13 and triggered into its unstable state by a pulse on line 19 from the second stage of counter 3, and according to the state of bistable 11 causes a pulse to be added or deleted from the gate circuit 2. Unit 13 is a pulse delaying and shaping unit comprising a monostable 14 set by 1-0 transitions of input signals; the output of monostable 14 sets a bistable 15 which is re-set by 1-0 transitions of the inverted input signals (on the un-numbered input line). After a delay of half a bit width the monostable 14 re-sets and passes a pulse to bistable 11 and to gate 16 which provides an output to unit 18 unless the initial 1-0 transition is followed by the reverse transition within half a bit width.
GB1554867A 1966-04-07 1967-04-05 Method and apparatus for timing pulse synchronisation Expired GB1148245A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH515666A CH447322A (en) 1966-04-07 1966-04-07 Method and device for clock synchronization, in particular for telecontrol systems

Publications (1)

Publication Number Publication Date
GB1148245A true GB1148245A (en) 1969-04-10

Family

ID=4288862

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1554867A Expired GB1148245A (en) 1966-04-07 1967-04-05 Method and apparatus for timing pulse synchronisation

Country Status (3)

Country Link
CH (1) CH447322A (en)
DE (1) DE1290952B (en)
GB (1) GB1148245A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766484A (en) * 1972-09-18 1973-10-16 Bell Telephone Labor Inc Detection of cycle slippage between two signals

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3036205A1 (en) * 1980-09-25 1982-05-06 Siemens AG, 1000 Berlin und 8000 München Digital data transmission between exchange and terminal - using rising edge of each logic one pulse for synchronising terminal with exchange
GB9125536D0 (en) * 1991-11-30 1992-01-29 Hydra Tools Int Plc Mineral cutter tip and pick

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1066609B (en) * 1959-10-08 Dr. phil. habil. Oskar Vierling, Ebermannstadt Circuit arrangement for synchronizing message receiving devices controlled according to the start-stop system in the event of temporarily disturbed start-up and blocking steps
DE880317C (en) * 1940-04-25 1953-06-22 Lorenz C Ag Double-sided, instantaneously acting fine control arrangement to maintain the synchronous and in-phase running of locally synchronized axes
DE899515C (en) * 1940-06-25 1953-12-14 Lorenz C Ag Device for achieving the correct phase position between two synchronously running axes
GB757612A (en) * 1953-11-03 1956-09-19 Standard Telephones Cables Ltd Improvements in or relating to synchronising arrangements in electric telegraph systems
DE1128460B (en) * 1960-09-07 1962-04-26 Siemens Ag Method and circuit arrangement for maintaining the synchronization of the transmitting and receiving devices in synchronous telegraph systems
DE1145667B (en) * 1961-09-08 1963-03-21 Siemens Ag Method for recognizing and eliminating the unstable phase position in the receiving device of synchronously operated telegraph systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766484A (en) * 1972-09-18 1973-10-16 Bell Telephone Labor Inc Detection of cycle slippage between two signals

Also Published As

Publication number Publication date
CH447322A (en) 1967-11-30
DE1290952B (en) 1969-03-20

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