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GB1145488A - Semiconductor device fabrication - Google Patents

Semiconductor device fabrication

Info

Publication number
GB1145488A
GB1145488A GB1566266A GB1566266A GB1145488A GB 1145488 A GB1145488 A GB 1145488A GB 1566266 A GB1566266 A GB 1566266A GB 1566266 A GB1566266 A GB 1566266A GB 1145488 A GB1145488 A GB 1145488A
Authority
GB
United Kingdom
Prior art keywords
silicon
mesas
wafer
mesa
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1566266A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of GB1145488A publication Critical patent/GB1145488A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C8/00Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

1,145,488. Semi-conductor devices. TEXAS INSTRUMENTS Inc. 7 April, 1966 [30 April, 1965], No. 15662/66. Heading H1K. An intermediate product from which mutually isolated semi-conductor components can be made consists of a mono-crystalline semiconductor wafer with at least one mesa on one face, and a support body, which is separated from the wafer at least in the region surrounding each mesa by a layer or layers of a material harder than the wafer material. In the preferred embodiment mesas 2 mils high are formed on an N+ silicon wafer by photoresist and etching steps and silicon carbide deposited on the resulting surface from a gaseous mixture of toluene and silicon tetrachloride in the carrier gas hydrogen. Amorphous or monocrystalline silicon of N, P or intrinsic type is then deposited to a depth of 7-8 mils. If desired a layer of molybdenum or tungsten is deposited before the carbide to provide a low resistance current path. In an alternative method silicon dioxide is thermally grown over the prepared surface of the wafer, and the silicon carbide deposited on top of it. A variant of this is to etch the dioxide from the inter-mesa areas and then deposit the carbide on the cleared areas through a silicon mask. In all cases the support body is next lapped down to the silicon carbide around the mesas which acts as a stop preventing the further lapping of the mesas which might otherwise occur in securing a flat surface on a warped body. The lapped surface is covered with oxide masking, which is removed over the centres of the mesas by photo-resist and etching steps. A pit is formed in each mesa by gas etching through the mask and is filled with higher resistivity N-type silicon by epitaxial deposition. Finally the base regions of transistors and resistive tracks and transistor emitter regions are formed in neighbouring mesas by successive masked diffusion processes and the resistors and transistors connected to form a logic circuit by depositing metal over an apertured masking layer and then etching it selectively to form the interconnections. Other hard materials such as alumina and boron may be used instead of silicon carbide.
GB1566266A 1965-04-30 1966-04-07 Semiconductor device fabrication Expired GB1145488A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US45230065A 1965-04-30 1965-04-30

Publications (1)

Publication Number Publication Date
GB1145488A true GB1145488A (en) 1969-03-12

Family

ID=23795943

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1566266A Expired GB1145488A (en) 1965-04-30 1966-04-07 Semiconductor device fabrication

Country Status (2)

Country Link
DE (1) DE1564832A1 (en)
GB (1) GB1145488A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2451636A1 (en) * 1979-03-14 1980-10-10 Licentia Gmbh PROCESS FOR PRODUCING A SEMICONDUCTOR-GLASS COMPOSITE MATERIAL

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2451636A1 (en) * 1979-03-14 1980-10-10 Licentia Gmbh PROCESS FOR PRODUCING A SEMICONDUCTOR-GLASS COMPOSITE MATERIAL

Also Published As

Publication number Publication date
DE1564832A1 (en) 1970-10-01

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