GB1131328A - Decoding circuit - Google Patents

Abstract

1,131,328. Decoders. INTERNATIONAL STANDARD ELECTRIC CORP. 28 July, 1967, No. 34817/67. Heading G4H. A circuit decoding a group of g (e.g. 70) n digit binary code combinations which may be divided into r (e.g. 10) classes such that each class includes only code combinations derivable from each other by cyclic permutation (e.g. one class comprises 01010101 and 10101010) includes a shift register R, to which the code combinations are fed, connected to a decoder D which decodes only r particular code combinations (i.e. one in each class) and an n position ring counter A, the combination code in register R being shifted until one of the r particular code combinations is obtained and decoded by decoder D to give a signal on one of its r outputs (d 1 -d 10 ), the ring counter A counting the number of shifts necessary and giving a signal on one of its n outputs, these two signals being fed to a decoding matrix S which then delivers a signal on one of its g outputs. In the embodiment described, the code combinations are 8-bit zero disparity codes derived from duration modulated satellite control signals.