GB1113883A - Improvements in or relating to electric waveform analysing apparatus - Google Patents

Abstract

1,113,883. Semi-conductor switching circuits. NATIONAL RESEARCH DEVELOPMENT CORPORATION. 7 Dec., 1965 [15 Oct., 1964; 12 Feb., 1965], Nos. 42149/64 and 6236/65. Heading H3T. [Also in Division G4] A signal analysing circuit gives a count of the total number of signal peaks, and a count of the number of such peaks which have occurred in each of a number of amplitude ranges. The circuit comprises a chain of tunnel diodes having different peak and valley values, which are successively switched from one state to the other, as the signal level varies. In one embodiment. Fig. 4, the rising flank of a waveform to be analysed sequentially switches tunnel diode chain Do to produce a train of output pulses at the collector of PNP transistor T1, the first pulse of the train switching bi -stable circuit TC to its SET state. The falling flank of a waveform sequentially resets the diode chain DS to produce a negative pulse train at the collector of NPN transistor T2. These pulses are inverted to produce a positive pulse train, the first pulse of which resets the bi-stable circuit, the output from which is fed to a counter. Instead of the bi-stable circuit being switched by the first of each train of pulses, counters (BC1, BC2), Fig. 5 (not shown), may be included in its set and reset circuits, so that switching occurs only after a predetermined number of pulses. In another embodiment, Fig. 7, the input signal to be analysed is applied directly to a first tunnel diode chain EF1, and via an inverter INV to a second chain EF2. As the input signal at 10, 11 rises the tunnel diodes in EF1 sequentially switch their state to produce a staircase output, which is differentiated to produce a pulse train the first of which sets a bistable circuit TC2. As the input signal falls a similar train of pulses is produced from EF2 the first of which resets the bi-stable circuit TC2, so that this circuit changes its state each time the signal passes through a peak. The " count pulse " output from TC2 is fed to a counter CT. The pulses from EF1 are also fed on line 40, Fig. 9, to a ring counter RGC having the same number of stages as there are tunnel diodes in the chain of EF1. Each time a peak occurs a " count pulse " signal is fed on line 41 to AND gates GA . . . GE, and an output is produced by the one of these gates receiving an input from counter RGC. to actuate an associated counter CA ... CE. The counter actuated thus corresponds to the amplitude range in which the peak occurs. The two chains EF1, EF2 are crosscoupled, so that the pulse train from one resets the other, gates 20, 21 being provided to inhibit false operation of the bi-stable circuit during reset. Circuit details of this embodiment are described with reference to Fig. 8 (not shown).