GB1046711A - Transistor inductor - Google Patents

Abstract

1,046,711. Transistor reactance circuits; automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. Jan. 22, 1965 [Jan. 24, 1964], No. 2890/65. Headings H3R and H4K. A transistor circuit, Fig. 1, simulates an inductor having high A.C. impedance but low resistance between the input 50 and ground. A PNP transistor 51 is normally forwardly biased by potentiometers 53-55, 56-58 when the input 50 is at a desired potential, the collector output being applied to a grounded emitter NPN transistor 52 whose collector is directly connected back to the input 50 which is also capacitively coupled at 54 to the base of transistor 51. The capacitor 54 may be variable to vary the inductor effect and the circuit shows positive or negative A.C. input impedance dependent on the relative value of resistor 55. A D.C. or low-frequency input at 50 is unaffected by the capacitor 54, is amplified by both transistors and increases or decreases correspondingly the conductivity of transistor 52 shunting the input so that the input impedance is low. Such an inductor circuit 61, Fig. 2 (not shown), may be used in the telephone system described in Specification 953,895 to provide a low resistance path to earth for the battery B1 via the constant current source 66, diode network 62 and diode 72. The secondary of the repeat coil 65, terminating the subscriber's line 60, is in this case capacitively coupled at 68 to the network 62 and thus the previous need for completing the D.C. holding path for the network 62 through the repeat coil secondary is avoided. The diodes 71, 72 together form a gate which is opened when a call involving subscriber line 60 is to be made.